What’s Next for Multi-Die Systems in 2024?

This article was originally published on Fierce Electronics.

It’s hard to imagine the level of systemic scale and complexity that is required to create a world that is truly smart. Applications such as ChatGPT, something we can’t live without, require massive amounts of data to function. The dataset of 300 billion words it was trained on, 60 million daily visits, and more than 10 million queries every day as of June 2023 are just the beginning. The more sophisticated technologies such as AI and high-performance computing (HPC) become, the greater the bandwidth and compute power they depend on.

Multi-die system architectures offer the means for innovation to continue to accelerate as Moore’s law slows, across areas from generative AI to autonomous vehicles and hyperscale data centers. While we are already seeing movement in this direction and will continue to see progress in 2024, uptake is nuanced, and design currently exists in a middle ground from 2D right up to 3D (even extending to 3.5D in some cases) according to performance, power, and area (PPA) requirements — or, more specifically, performance, power, form factor, and cost.

The smart future relies on multi-die system design, but it will need assistance to become a widespread reality in the coming year and beyond. Here are four of the top multi-die system design predictions coming in 2024.

The Multiple Stages of Multi-Die System Adoption

It is not surprising that data-hungry applications are the major drivers of multi-die system packaging such as 2.5 and 3DIC design. We can expect data centers to be the most enthusiastic “users” for the foreseeable future given the volume and complexity that are inherent to the sector. Other areas such as mobile are on the cusp of utilizing multi-die system design but are likely to be more selective, opting for different stacked layers and nodes depending on needs. This likely means chip design engineers for mobile applications will opt for packaging such as organic substrates.

Industries like automotive, which typically source components from a wide array of vendors, are likely to continue using 2.5D packaging, taking a chiplet-based approach. This method ensures that electronic control unit (ECU) parts are readily available and can be easily assembled on a substrate such as an interposer. Mixing and matching is a fact of life for chips used in vehicles; at the same time, this practice would likely benefit from a higher degree of standardization.

Commonality Amid Complexity

A major stumbling block to the adoption of multi-die systems that engineers will continue to struggle with in 2024 is the complexity of vertical integration. Where HPC data centers have the wherewithal to manage stacking, other industries do not. Not being vertically integrated and relying on the ecosystem, as is the case in automotive, makes multi-die design a challenge as it increases the number of requirements for smooth functioning.

When it comes to 3D stacking, the main challenges include thermal analysis, power distribution planning, cooling systems, and manufacturing requirements. Complex as it is, 3D represents the future, and the ecosystem must evolve to enable it. As stacking becomes more widespread, UCIe — already the preferred interface for 2.5D — will advance accordingly in the coming year and beyond. Complexity can be further simplified by two key factors: a common language and clear rules. Commonly accepted terms for the components of a 2.5D or 3D design bring uniformity to the proceedings and make it easier to construct a system with multiple partners.

Rules, and a standard means of describing them, are essential for multi-die system innovation to succeed. Just as vehicles on a freeway must obey the signs, rules will continue to govern the application of silicon, whatever form it may take. Features such as standardized testing and reference flows will make all aspects of the stacking process, including manufacturing, more straightforward.

Multi-Die Systems Are Not Unlimited

As multi-die system design advances, some limits are likely to persist. For one thing, we expect high bandwidth memory (HBM) to remain external in 2024. Depending on bandwidth and thermal requirements, we may see it move closer to the chip, but its off-chip designation is unlikely to change.

In terms of stacking, the sky is not the limit: In the current environment, three to four layers are generally the upper boundary (with a few exceptions). This is due to not only constrictions in power supply but also in manufacturing and reliability. As with a skyscraper, extreme height adds to the list of structural issues to contend with. A high stack entails more manufacturing steps and more risk, and achieving it with confidence will take time. To be sure, the industry is working toward it. Getting there calls for the widespread embrace of end-to-end automation.

2024 will be the year we become much closer to widespread multi-die system adoption that will spark many new innovations in both chip design and the end applications themselves. However, there will be challenges that will require collaboration from all players in the semiconductor ecosystem to overcome the immense complexity of multi-die system design and move toward the smarter world and future we know is possible.