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Verification IP for LPDDR2
Synopsys Verification IP (VIP) for the JEDEC LPDDR2 provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification convergence on LPDDR2 based designs. VIP can be integrated, configured and customized with minimal effort. Testbench development is accelerated with built-in verification plans, example tests, and functional coverage. VIP is natively integrated with Verdi® Protocol Analyzer, a protocol-centric debug environment that gives users graphical view of VIP operations, transactions, and memory content view for easy and fast debug.
Memory Model Certification
Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.
Highlights
- Native SystemVerilog/UVM
- Runs natively on all major simulators
- Runtime JEDEC and vendor part selection
- Verification plan and coverage
- Built-in protocol and timing checks
- Verdi protocol-aware debug
- Overriding timing parameters
- Backdoor memory access
- Bypass/fast initialization
- Error injection & exceptions
- Trace files and debug ports
- Configuration creator GUI
Features
JESD209-2F JEDEC LPDDR2 specification
64Mb to 8 Gb densities and x8, x16 and x32 wide SRAM devices
All data rates (200-1066 Mbps)
Memory Densities (64Mb to 32Gb)
Write leveling and ZQ calibration
Power off sequence, self-refresh, deep power down, partial array self-refresh
DFI monitor support
All commands
All mode registers (WL/RL,other fields)
All the core timings
Bypass and fast-memory initialization reduce simulation time
Error injection and exception to control behavior
Easy method to vary timing parameters and clock
Extensive protocol and timing checks
Checks can be enabled or disabled either individually or in a group
Complete functional coverage
Back annotation of coverage
Backdoor access to memory contents and mode registers
Readable trace log file to debug and analyze memory transactions
Board delay modeling
JEDEC and vendor parts support
Support to specify part details using runtime parameters without re-compilation