The Synopsys Seminars are a forum for members of the electronic design community to get the latest information on design automation solutions, methodologies and standards. Intended for IC design, process and verification engineers and managers, these FREE technical seminars are a resource to help accelerate innovation.
Galaxy Design Seminars
Worldwide schedule commencing May 2014
Attend a FREE Synopsys seminar to learn about new capabilities available with the most recent Galaxy Design Platform tool releases and how to use them effectively to increase design productivity and achieve performance, power, and area and manufacturability goals. Seminar topics include RTL synthesis, design-for-test (DFT), physical design and verification, and signoff.
Learn More >>
May 2014 – September 2014
The Verification Seminar is a one-day technical seminar providing an overview of Synopsys' functional verification technologies and how the recently introduced Verification Compiler offers key technologies and capabilities to help manage verification complexity. The seminar will also delve into several advanced verification flows comprising Synopsys technologies, including static and formal verification, simulation, advanced debug, coverage-driven verification, verification IP, emulation, and FPGA prototyping.
Register Now >>