Webinars 


Accelerate DesignWare IP Driver Development for ARMv8-based Designs with Virtualizer Development Kits
Understand how Virtualizer™ Development Kits (VDKs) can be used to accelerate DesignWare® Interface IP driver development and integration into a 64-bit ARMv8 Linux software stack.
Achim Nohl, Technical Marketing Manager, Synopsys
Apr 16, 2015

"Shift Left" Functional Safety for Automotive System Development
Since safety is one of the most challenging problems in the automotive industry, we will look at fault mode and effect analysis (FMEA) using virtual prototyping and physical modeling and simulation.
Nicolas Brown, Corporate Applications Engineer, Synopsys; Victor Reyes, Technical Marketing Manager, Synopsys
Apr 15, 2015

TSMC's Use of Synopsys STAR Memory System: Features and Capabilities
TSMC describes their memory test challenges in manufacturing billions of chips each year and the memory modeling and diagnostic features that enable efficient silicon bring-up and characterization.
Dr. Saman Adham, Senior Manager, BIST & ASIC Design Group, TSMC; Prasad Saggurti, Product Marketing Manager, Synopsys
Apr 14, 2015

Picking up the pieces: self-contained verification platforms for the modular smartphone era
In the framework of Mobile platforms, learn how source code testsuites provided with Verification IP enable verification engineers to quickly generate diverse permutations of random/constrained random transactions that stress test the systems and subsystems, contributing to "Shift Left" of the verification time and ensure bug free designs.
Nitin Agrawal, CAE Manager, Verification Group, Synopsys
Apr 07, 2015

Choosing the Optimal Multiprotocol PHY IP for Your SoC
Learn about the architectural differences between enterprise and consumer multiprotocol PHY and the optimal PHY solution for your SoC that meets your specific design requirements.
Rita Horner, Sr. Technical and Product Marketing Manager, Synopsys
Apr 02, 2015

Meeting 90-nm to 10-nm Physical IP Design Requirements for Wearables and Application Processors
Understand the 90-nm to 10-nm technology process and IP requirements for wearable/IoT devices and mobile application processors.
Navraj Nandra, Sr. Director of Marketing for the DesignWare Analog/Mixed Signal IP, Synopsys
Mar 31, 2015

Design, Test & Repair Methodology for FinFET-based Memories
Understand the challenges associated with testing FinFET-based memories and new methods to address FinFET-specific defects.
Dr. Yervant Zorian, Chief Architect and Fellow, Synopsys
Mar 03, 2015

An Approach for Efficient IP Reuse in a Hierarchical UPF Methodology
This webinar will help you understand a Liberty-based approach for effective IP reuse in implementation of a multi-voltage hierarchical design using the IEEE 1801 (UPF) standard.
Viswanath K. Ramanathan, Corporate Applications Engineer, Synopsys; Mary Ann White, Director of Product Marketing, Synopsys
Feb 26, 2015

Designing SoCs for USB Type-C Products
Understand the USB Type-C specification from an SoC designer’s perspective, how to add USB Type-C to existing designs and recommendations for new SoC architectures.
Morten Christiansen, Technical Marketing Manager, Synopsys; Gervais Fong, Senior Product Manager, Synopsys
Feb 18, 2015

STMicroelectronics: Successful Last-minute Functional ECO Implementation with Formality Ultra
STMicroelectronics describes how they used Formality® Ultra to meet their tight release schedule for their ARM® core based designs despite having to implement multiple functional ECOs late.
Kailash Digari, Group Manager CPU-GPU design, STMicroelectronics; John Lehman, Senior CAE Manager, Synopsys
Feb 05, 2015

Successful GPU IP Implementation on Synopsys HAPS Platforms using ProtoCompiler
Learn how Synopsys ProtoCompiler and debug tool coupled with the flexible HAPS prototyping systems helps GPU developers tackle implementation of complex GPU IP and its end applications.
Andy Jolley, Senior Staff Application Consultant, Synopsys
Feb 04, 2015

Getting the Most out of IP-based Designs with Synplify FPGA Design Tools
Learn how to streamline and automate your IP-based FPGA design flow using Synopsys FPGA design tools, allowing you to attain your design objectives within the framework of how IP will be delivered.
Parminder Gill, Engineering Project Leader, FPGA Implementation, Synopsys
Feb 03, 2015

Simulation Acceleration with Native SystemVerilog Transactors
Learn how to build UVM/SystemVerilog testbenches that can be directly reused or easily extended when transitioning from simulation to emulation.
Parag Goel, Senior CAE, Verification Group, Synopsys
Jan 29, 2015

Automate Low Power Verification and Implementation Flow with VC Apps
UPF imported into Verdi's database provides valuable information to understand relationships between logic designs to power its intent. Learn how VC Apps APIs allows users to check if the design meets the requirements of low power design rules, and helps automate the implementation of low power design structure.
Rich Chang, Product Marketing Manager, Debug, Synopsys; Paul Huang, Corporate Application Engineer (CAE), Synopsys
Jan 28, 2015

Achieving Energy Efficiency for IoT Designs
Learn how new investments in IP help improve system power usage and energy efficiency and enable added functionality for IoT applications including wearable and machine-to-machine devices.
Ron Lowman, Strategic Marketing Manager for IoT, Synopsys
Jan 27, 2015

How to Optimize your Application-Specific Processor (ASIP)
Attend this webinar to gain a demonstration of the architectural exploration flow based on IP Designer, Synopsys' ASIP design tool.
Werner Geurts, CAE Manager, Synopsys
Jan 21, 2015

FinFETs For Your Next SoC: To Move or Not To Move? (Mandarin)
Learn about the benefits and challenges of moving from a planar CMOS process to FinFET and how DesignWare embedded memory and logic library IP can enable this move.
Xueheng Ren, Senior Field Application Engineer, Synopsys
Jan 15, 2015

Understanding USB 3.1’s Physical, Link & Protocol Layer Changes
Get an in-depth look at the changes in the USB 3.1 specification’s physical layer, link layer, protocol layer, and hub.
Mattew Myers, Sr. Staff R&D Engineer, Synopsys
Jan 13, 2015

Avoiding the Common Pitfalls of ARM-based Cache-coherent Verification and Performance Analysis
Synopsys will cover how verification IP for AMBA enables users to generate correct and interesting coherent stimulus for cache coherent SoC verification. This will include the complexities of configuration, stimulus, coverage and checking, as well as how to address the common verification pitfalls.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Tushar Mattu, Corporate Application Engineer (CAE) for Verification Group, Synopsys
Dec 03, 2014

LPDDR4 Multi-Channel Architecture
Learn about connecting multiple channels of DRAM, tradeoffs in SoC floorplans, logical to physical addressing, connecting to on-chip buses, and low-power design methods for LPDDR4.
Marc Greenberg, Director of Product Marketing for DDR Controller IP, Synopsys
Dec 02, 2014

Simplify Sensor and Actuator Functionality for your IoT Solution
Learn how increasing system complexity as sensor fusion functions in IoT apps expand to include biometric control features can be addressed with a tightly integrated sensor and control IP subsystem.
Rich Collins, Product Marketing Manager, Synopsys
Nov 12, 2014

Take Control of Your Flow: Getting Started with Your First VC Apps
VC Apps, a programming interface available with Verdi, provides direct and open access to information from Verdi’s databases, analysis engines, and GUI components to customize, innovate or integrate within the Verdi debug environment. Verdi users have the power to maximize their effectiveness by using pre-built VC Apps or writing custom automation apps, scripts or programs. Learn how VC Apps APIs allow users to quickly get started writing programs, and provide many valuable ready-to-use apps installed in the Verdi package.
Rich Chang, Product Marketing Manager, Debug, Synopsys; Paul Huang, Corporate Application Engineer (CAE), Synopsys
Nov 11, 2014

High-Speed Embedded Linux Processing on an Embedded Power Budget
This webinar will look at a new high-speed processor implementation that can bring high-performance to your Linux-based embedded designs while significantly reducing power consumption.
Mike Thompson, Sr. Product Marketing Manager, Synopsys
Nov 06, 2014

HSPICE Tips & Tricks Webisode Series
Learn from Synopsys applications engineers how to get the most out of HSPICE analysis. Topics will include how to most effectively use S-element, eye diagrams, IBIS-AMI, RUNLVL, and more. New mini webinars will premiere monthly.
Ted Mido, Principal Engineer, HSPICE R&D, Synopsys
Nov 03, 2014




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