ARM® Techcon™ 2013 

Fast track your ARM-based design with Synopsys 

October 29 – October 31
Santa Clara Convention Center

See how Synopsys’ optimized solutions and expertise in creating advanced System-On-Chips (SoCs) with ARM® processors and AMBA® interconnect is enabling companies to accelerate design innovation and time-to-market for their next-generation ARM Powered® products.

Visit us at Booth # 612 in the convention center and attend one of our Conference/Sponsored sessions to learn more—descriptions are below. To register for one these sessions, please go to the ARM TechCon page.

Attend one of our Synopsys Sponsored Sessions to enter drawings to win one of two Apple iPad minis!

ARM Technology Conference 2013


Sponsored Session and Conference Sessions

Conference Session — Grand Ballroom A

2:30 pm – 3:20 pm

Late-Stage Leakage Recovery Strategies for Cortex-Based Designs with Lynx
Terence O'Brien, Corporate Application Engineer, Synopsys
(Open to those with ARM TechCon Conference passes)

Optimized processor-specific flows play a critical role in achieving ARM processor performance and power goals. To that end, Synopsys has expanded the availability of pre-optimized high-performance and low-power Lynx flows for ARM Cortex-A7, -A9 and -A15 processors and accelerate core hardening. This paper discusses late-stage leakage-power-recovery techniques and strategies leveraging:
  • Final-stage leakage-recovery in an IC compiler
  • The new PrimeTime ECO leakage flow
  • Multichannel libraries for leakage-power recovery

These methodologies, as a part of a complete RTL-to-GDSII design solution available in the Lynx Design System, can help you achieve your power targets while maintaining design performance

ARM Sponsored Session — Mission City Ballroom B1

1:15 pm – 2:30 pm

Samsung, ARM and Synopsys Collaborate to Tape-out and Analyze the Production Qualification Vehicle for 14-nm FinFET Featuring ARM® Cortex®-A7 and Cortex-A15 Processors

In this session, you will learn about the Samsung, ARM and Synopsys collaboration to tape-out the production qualification vehicle for 14-nm FinFET featuring ARM Cortex A7/A15 processors. We will introduce the enabling technologies in and best practices with Synopsys Design Compiler and IC Compiler used to achieve GHz+ clock speed within the tight product schedule. These include advanced synthesis for better predictability, as well as diverse techniques for faster timing, reduced power and congestion, tighter post-route correlation and more. The session will also highlight the collaboration for 14nm manufacturing compliance that was essential for this 14nm FinFET-based SoC success.

Sponsored Sessions — Mission City Ballroom M2

10:30 am -11:20 am

Implementation and Virtual Prototyping of a 2.6 GHz ARM® Cortex®-A15 Processor in a Cortex-A15/Cortex-A7 MPCore big.LITTLE Processing SoC
Seiji Goto, Manager, Imaging Solution Division, Advanced Products Business Unit, Fujitsu

Fujitsu recently taped out a complex visual computing SoC with a dual-core Cortex-A15 / dual-core Cortex-A7 MPCore big.LITTLE processing subsystem and ARM Mali T624 CPU. This session will highlight enabling technologies in Design Compiler and IC Compiler which, together with the Synopsys high performance core (HPC) methodology, delivered an impressive 2.6 GHz frequency on the Cortex-A15 processor sub-system. These technologies include improved predictability by using Synopsys physical guidance (SPG) and layer-aware optimization, clock mesh to reduce on-chip variation and skew and Final-stage Leakage Recovery to minimize leakage power. The session will also provide an overview of Fujitsu’s use of the Synopsys Virtualizer™ Development Kit (VDK) for the big.LITTLE configuration, used to accelerate software development.

11:30 am – 12:20 pm

Cache Coherent Interconnect Optimization for Micro-server Multicore SoCs
Pat Sheridan, Senior Staff Product Marketing Manager, Synopsys

Broadband video, social networking, cloud-based services – these types of residential, business, and mobile networking applications are driving a tremendous increase in traffic and placing significant demands on the data center to improve system efficiency and reduce space, cost, and power. This session addresses challenges associated with HW-SW partitioning and cache coherent interconnect optimization for the micro-server SoC and how early architecture simulation with Synopsys Platform Architect helps achieve the right system performance, power, and cost.

1:30 pm – 2:20 pm

Easing Bring Up of UEFI-firmware Software for ARMv8 Servers
Tom De Schutter, Senior Product Marketing Manager, Synopsys

In this session we will introduce tools and methods for OS/firmware bring-up of DesignWare IP in context of ARM-based data center software stacks. We will focus on the Unified Extensible Firmware Interface (UEFI) and Advanced Configuration and Power Interface standards. The session will cover virtual prototype usage to ease development tasks for early software bring-up, debug and test through UEFI aware analysis. A case study will be presented centered on a bringing up an ARMv8 Linux-KVM based LAMP server software stack.

2:30 pm – 3:20 pm

Meeting the Challenge of ARM® AMBA® 5 CHI Verification Using Discovery Verification IP
Neill Mullinger, Product Marketing Manager, Synopsys

AMBA 5 CHI (Coherent Hub Interface) is a packet-based protocol developed to provide high-performance, cache coherent communication between ARM Cortex A50-series processors. It is used with other ARM AMBA protocols to create cache-coherent SoC interconnects that encompass memory subsystems, signal processing, graphics processing and off-chip communication. The current generation of VIP’s is running out of steam to provide the performance, productivity and features to verify the design as RTL is incrementally integrated into the system. This session will show how next-generation SystemVerilog VIP enables the rapid creation of a multi-protocol verification environment for an AMBA based SoC including CHI, ACE-Lite, and other AMBA interfaces. The tutorial will cover stimulus, system-wide data integrity checking, performance analysis, performance checking, protocol-aware debug, and coverage closure.

3:30 pm – 4:20 pm

Energy efficient implementation of ARM® Cortex™-A57/-A53 processor cores in FD-SOI process technology
David Jacquet, Senior Principal Engineer, Design & Architecture for Energy Efficiency, STMicroelectronics

In this session STMicroelectronics shares its approach to delivering optimized energy efficient solutions for the SoC market. Starting with an overview of the Fully Depleted Silicon On Insulator (FD-SOI) process technology as an enabler for high performance / low power design, the session will focus on ST’s low power architecture for the latest ARM® processors – Cortex®-A57 and -A53. Highlights from the low power implementation and verification methodology developed with Synopsys, including results and best practices, will also be presented. The session will conclude with a preview of ST’s process technology and ARM-core based SoC product roadmap.