SNUG 2012 Keynote Videos 

 Critical Mass Through Collaboration
Dr. Aart de Geus, Synopsys CEO & Chairman of the Board - SNUG Silicon Valley 2012
In a design ecosystem increasingly influenced by software and systems development, massive verification demands, and the boundaries of physics, engineers have a wonderful new set of problems to solve! Yet the principles they will use to innovate their way to exciting solutions and products remain as fundamental and universal as the reality of the Golden Ratio itself. With the aid of some of these principles, Aart will talk about what new strategies and methodologies semiconductor players will need to achieve the critical mass necessary to craft productive and creative solutions within a design ecosystem complexity that surpasses anything seen yet in human history.

 Partnering for Low Power
 
John Cornish, Executive Vice President, ARM  - SNUG Silicon Valley 2012
To fully exploit the next generation of process technology, a system approach to low power is needed. The challenge is to avoid 'dark silicon’ which is prohibitively expensive to 'light up' from an energy point of view. To mitigate this, all aspects of system design have to be optimized, even though each may only make a small contribution to energy efficiency. What matters is the product of all of these improvements, from transistor level through SoC architecture and up in to the software stack. By working in partnership, engineers from across the industry can apply new techniques to reduce power in all parts of the system. This presentation will describe work ARM is doing in physical IP, interconnect, and processor sub-systems to enable energy efficient systems. It will also discuss the importance of system profiling and analysis, and definition of new industry standards.

 3D FinFET - New Structure Extends the Life of the Transistor!
Dr. Chenming Hu, Professor Emeritus UC Berkeley & Former CTO TSMC - SNUG Silicon Valley 2012
MOSFETs are undergoing the most drastic transformation in nearly 50 years. What’s driving this change and how will the move to 3D FinFET impact IC technology? What are these new transistors? What demands will they place on EDA tools and the design community? Professor Hu will provide insight into the driving factors behind these new transistors and how these transistors will enable the continued use of existing infrastructures of circuit and system designs, as well as device fabrication, for decades to come.

  
 SNUG 2012 Call for Papers
John Busco of NVIDIA and SNUG Silicon Valley Technical Chair. 
If you have used Synopsys technology to overcome difficult design issues, we want to hear from you! Please share your experience at one of the 15 user group events Synopsys hosts annually. The success of SNUG depends on the active participation of users who are willing to share their experiences with others. If you want to share an experience with Synopsys tools you are encouraged to submit a paper and present at SNUG in 2012.


User Paper:  Migrating from C++ to SystemVerilog: Anatomy of a Hybrid Testbench
Brian R. Folsom of Cavium Networks - SNUG Boston 2011
Migrating a complex verification environment from C++ to SystemVerilog is a multi-step process that involves many factors. To be successful you must first clearly envision your desired end result and then develop a detailed plan to get here. This paper provides an overview of the issues involved and presents a high-level migration strategy.



 

User Paper:  SystemVerilog Functional Co-Simulation
Todd Honan & Stuart Patterson of Analog Devices - SNUG Boston 2011
This paper will discuss our experience using SystemVerilog, VCS and CustomSim to functionally verify the pad circuitry used for a DSP processor. We’ll talk about how we can easily modify a SystemVerilog test bench to perform three different verifications: 1) the functionality of the Verilog equivalent model, 2) the functionality of the analog circuitry as represented by an HSPICE netlist, and 3) the functional equivalence of the verilog and HSPICE design representations. In addition, we’ll show a detailed example of our VCS CustomSim co-simulation setup, which takes into account the multiple power domains and tri-state signals present in out pad circuitry.




 

User Paper:  Multi-Tool Formal Verification
Jonathan Wolfe of Samsung - SNUG Austin 2011
Some complex designs exceed the capabilities of any single formal verification tool to completely verify them. These designs must be partitioned and verified in piecemeal manner. I will describe the successful verification of RTL which required 3 formal tools (Formality, ESP-CV, and a sequential equivalence checker) and an intermediate layer of RTL edits to achieve complete verification.