Through our Curricula Advisory Board, Synopsys works closely with a team of academic experts to develop microelectronic design curriculum for Synopsys University Program members. Each full-semester course contains 15 weeks of material including syllabus, lectures, labs, home work and exams. Synopsys tools are used and applied in each lab for a thorough and practical understanding of theoretical concepts introduced in each of these courses. This courseware can be used as a new course or to supplement content in an existing course as needed.
Synopsys also offers curriculum support modules which vary in length and include more lectures and Synopsys tool training materials than the full-semester courseware.
All courseware described below may be downloaded from the Synopsys University Program Member Only website (requires SolvNet ID and password). If you are not yet a member of the Synopsys University Program, but want to know more, please contact the program administrator for your region.
| Curriculum Support Modules: Workshops and Lectures|
- SystemVerilog/Verification Methodology Manual (VMM)
- SystemVerilog Verification Tutorial (SFSU) - New!
- Universal Verification Methodology - New!
- Verilog HDL Basics
- TCAD Course
- TCAD for VLSI Design
- TCAD Short Course
- TCAD Quick Start Guide
- 90nm Digital Design Workshop
- ASIC Design Flow Tutorial Using Synopsys Tools
- Digital Design Flow Based on PowerPC 405 Processor
- Full Custom IC Design Flow Using Synopsys Custom Tools (SFSU)
- IC Synthesis Based on ARM Cortex-MO DesignStart Processor - New!
- Software Methodology Using Custom Designer
- Synopsys Design Flow Tutorial
- Synopsys IC Design Flow Based on 90nm Generic Library (SAED 90nm EDK)
- Synthesis Basics - New!
- UPF Workshop
| Short Lectures/Labs|
- Circuit Simulation:
- Circuit Simulation: Transient Analysis
- Techniques for Circuit Simulation
- Thermal and Electro-Thermal Simulation: Achievements and Trends
- Low Power Design:
- Low Power Methodology Manual for 90nm
- Low Power Methodology Manual for 32/28nm - New!
- Subthreshold Design and Implementation (RIT)
- Verification Methodology Manual for Low Power (VMM-LP)
- Multi-threaded SPARC core verification using SystemVerilog Testbench
- Synthesizing 64-bit OpenSPARC multi-threaded core on FPGA with Synopsys Synplify tool chain
- Synthesizing a Design Using the 90nm Technology Library
- Addressing Process Variations and Patterning Issues in VLSI Designs (UCLA)
- Advanced RTL Verification Techniques
- Basic Perl Programming
- Design Methods of Nanoscale Memories
- Design Methods of Nanoscale Sigma-Delta Modulators
- Embedded Systems Design
- How to Create an Interoperable PDK
- Introduction to Verilog HDL - Updated!
- Logic Simulation with Consideration of Destabilizing Factors
- Nanoscale Low Power Digital Standard Cell Library Tutorial
- Physical Verification Runset Development
- Power-Performance Optimization of Digital Circuits and Systems
- Process Variation Aware Design
- Sequential Elements - Updated!
- Signal and Power Integrity: Current State and New Approaches
- Statistical Techniques for Timing Analysis: Current State and Trends
- TCAD Microelectronic Labs (IIT)
| Tool Training|
- * FPGA:
- Advanced FPGA Synthesis using Synplify Pro and Synplify Premier
- Advanced FPGA Debugging with the Identify Tool
- * ASIC Prototyping:
- ASIC Prototyping with the Certify® Tool
* Requires SolvNet ID and password.
- * Synphony Model Compiler:
- Advanced Algorithm Implementation with Synphony Model Compiler
- Training Kits: (Purchase required)
- Synplicity IEEE-1364 Verilog University Kit
- Synplicity IEEE-1076 VHDL University Kit