The Synopsys Seminars are a forum for members of the electronic design community to get the latest information on design automation solutions, methodologies and standards. Intended for IC design, process and verification engineers and managers, these FREE technical seminars are a resource to help accelerate innovation.
Advanced Verification for Mixed Signal System on Chip
July 16, 2014
Consumer electronics continues to drive technology convergence. As a result, a growing proportion of SoCs includes digital and analog blocks from internal and third-party IP sources. The time and compute power required to verify these complex mixed-signal SoCs may exponentially increase the total cost of design. As mixed-signal SoC complexity grows, there is a new verification crisis on the horizon that requires additional focus on the overall verification methodology. This FREE seminar will offer an academic and industrial perspective on these verification challenges.
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Galaxy Design Seminars
Worldwide schedule commencing May 2014
Attend a FREE Synopsys seminar to learn about new capabilities available with the most recent Galaxy Design Platform tool releases and how to use them effectively to increase design productivity and achieve performance, power, and area and manufacturability goals. Seminar topics include RTL synthesis, design-for-test (DFT), physical design and verification, and signoff.
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May 2014 – September 2014
The Verification Seminar is a one-day technical seminar providing an overview of Synopsys' functional verification technologies and how the recently introduced Verification Compiler offers key technologies and capabilities to help manage verification complexity. The seminar will also delve into several advanced verification flows comprising Synopsys technologies, including static and formal verification, simulation, advanced debug, coverage-driven verification, verification IP, emulation, and FPGA prototyping.
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Synopsys’ HAPS-70 and HAPS-DX FPGA-Based Prototyping Systems Deliver 3x Prototype Performance
April 2014 – October 2014
Join Synopsys for a half-day seminar, including a networking lunch-and-learn, about the state-of-the art in FPGA-based prototyping based on high-capacity, high-performance Xilinx® Virtex-7 FPGAs. Learn how the latest multi-FPGA implementation software and new multi-FPGA debugging capabilities help to bring-up designs faster and accelerate availability for software development tasks. Understand new pin-sharing via high-speed multiplexing that improves interconnection performance up to 3 times. Understand how the combination of Synopsys design automation software, FPGA prototyping hardware and DesignWare IP help you to conquer prototyping needs up to 144M ASIC gates from small design IPs to multi-processor driven SoCs with numerous real world interfaces.
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