Webinars 


Accelerated Power Analysis with Synopsys Verdi Technologies (Part 4 of 4)
In this session, learn how to enable early and accurate power estimation by using RTL simulation results to generate gate-level simulation data, without the need for gate-level environment bring up; and how to increase speed up to 60% with the new Verdi Power Analysis Acceleration tool.
Vaishnav Gorur, Product Marketing Manager, Verification Group; Chun Chan, R&D Director, Verification Group, Synopsys, Inc.
Oct 05, 2016

Comprehensive Power Optimization Solution for Faster RTL Signoff (Part 3 of 4)
In this webinar, we will discuss how SpyGlass Power delivers an integrated early power analysis and exploration solution that includes: estimation, profiling, reduction and exploration.
Kiran Vittal, Product Marketing Director, Verification Group; Ken Mason, Corporate Applications Engineer, Verification Group, Synopsys, Inc.
Sep 21, 2016

Catch low-power simulation bugs earlier and faster with Verdi Power-Aware Debug (Part 2 of 4)
In this webinar, we will demonstrate how Verdi Power-Aware Debug greatly simplifies low-power debug and identifies potential design-killing bugs earlier and faster, with a unified and comprehensive view of the design and its power intent.
Vaishnav Gorur, Product Marketing Manager, Verification Group; Archie Feng, Corporate Applications Engineer, Verification Group, Synopsys, Inc.
Aug 31, 2016

Addressing Low Power Verification Challenges with Advanced Static Checking and Native Low Power Simulation (Part 1 of 4)
In this session, we will discuss UPF based static and dynamic verification techniques to address these challenges. We will also discuss the problems addressed by Synopsys’ VC LP and VCS NLP tools, to streamline the entire verification process.
Kiran Vittal, Product Marketing Director, Verification Group; Amol Herlekar, Sr. Staff Engineer, Verification Group, Ankush Bagotra, Staff Engineer, Verification Group, Synopsys, Inc.
Aug 10, 2016

Speed Software Development and IP Validation for ARMv8-based SoCs with Juno ARM Development Platform
This webinar introduces the new HAPS adaptor to connect a Juno ARM® Development Platform (ADP) to a Synopsys HAPS® Prototyping System or DesignWare® IP Prototyping Kit .
Achim Nohl, Technical Marketing Manager, Synopsys; Hugo Neto, Technical Marketing Manager, Synopsys
Jul 21, 2016

Time-travel in a SystemVerilog/UVM world – Interactive Testbench Debug Unleashed!
In this Synopsys webinar, we will show how interactive debug is ushering in a new era in testbench debug. Specifically, you will learn: how interactive and reverse interactive debug capabilities allow you to quickly root-cause and debug simulation failures; how what-if analysis improves TB debug efficiency by combining diagnosis and cure into a single step; how to navigate and effectively debug a UVM-based testbench
Vaishnav Gorur, Product Marketing Manager, Verification Group; and Mansour Amirfathi Sr. CAE Manager, Verification Group, Synopsys, Inc.
Jul 20, 2016

Successful SoC Implementation of USB Type-C and DisplayPort Alt Mode (Chinese)
This webinar discusses how to integrate USB Type-C and DisplayPort functionality, including solving critical hardware and software partitioning challenges.
Tom Liu, Field Application Engineer, Synopsys
Jul 19, 2016

Foundation IP for Automotive ICs: What Do You Need?
Learn what to look for when selecting Foundation IP for your automotive IC. Your PPA requirements are a given — learn about specific automotive requirements such as ISO 26262, TS 16949, zero DPPM & more
Prasad Saggurti, Senior Manager, Foundation IP Product Marketing, Synopsys
Jul 19, 2016

Selecting the Correct Mathematical Format to Achieve Design Precision
Learn about mathematical requirements for your targeted applications as well as new formats for use in hardware mathematics that can help you make clear design trade-offs and achieve design precision.
Kiran Kumar, Corporate Applications Engineer, Synopsys Inc.
Jul 14, 2016

Programmable Accelerators for Modern SoCs: When Hardware Accelerators Also Require Flexibility
Learn about the power of Application-Specific Instruction-Set Processors (ASIPs) and the growing need for more flexible, programmable accelerators for SoC designs.
Steve Cox, Sr. Manager, Business Development, Synopsys, Inc.
Jul 13, 2016

Test & Repair of SoCs for Functional Safety Applications (Chinese)
Learn about diagnosis, debug and self-test and repair solutions for memories, logic, AMS and interface IP blocks for automotive requirements to satisfy key criteria like low DPPM.
Qiuer Huang, STAR Memory System FAE, Synopsys
Jul 12, 2016

Securing IoT Systems with a Root of Trust (Chinese)
Security is critical to the success of IoT SoCs and must be an early design consideration. This webinar discusses IoT security threats and use cases requiring a secure root of trust.
Tom Liu, Field Application Engineer, Synopsys, Inc.
Jul 05, 2016

Enabling Machines to See with Efficient Embedded Vision Processors
Learn how Synopsys’ new embedded vision processor family with advanced vision capabilities can enable powerful and flexible vision solutions for your next-generations SoCs.
Michael Thompson,Sr. Product Marketing Manager for ARC and EV Processors, Synopsys, Inc.
Jun 29, 2016

Samsung and Synopsys 14nm Physical Verification in IC Validator and In-Design with IC Compiler II
Samsung and Synopsys together present a webinar on the manufacturing and physical verification challenges and solutions at 14nm.
KK, Lin, Director of Foundry Design, Samsung; Jonathan White, CAE Directory, Synopsys, Inc.
Jun 28, 2016

STMicroelectronics Sees Smarter, Faster Sign-off Cycles with Latest StarRC
STMicroelectronics will share their experiences with performance and efficiency advantages seen with the latest releases of StarRC and how they are helping ST to roll out their own products.
Raphael Gras, Sr. Digital Sign-off CAD Engineer, STMicroelectronics
Jun 23, 2016

Accelerate Development of Powertrain ECUs with Virtual Hardware
This 60-minute Webinar will provide an overview of virtual hardware ECUs and how to integrate them into the automotive system development process to manage these challenges.
Marc Serughetti, Business Development, Synopsys, Inc.
Jun 21, 2016

Enabling ISO 26262 Compliance with Synopsys’ Automotive Safety Verification Solution
This webinar will provide an overview of the concepts, requirements, and approaches for automotive IC designers and verification teams to understand what’s needed for ISO 26262 compliance for safety-critical SoCs and IP blocks. Capsule Module: Enabling ISO 26262 Compliance with Synopsys’ Automotive Safety Verification Solution
Brian Davenport, Staff Engineer, Synopsys’ Verification Group; David Hsu, Director of Product Marketing, Synopsys’ Verification Group
Jun 16, 2016

Double the Value - Accelerated SoC Verification AND Earlier Software Bring-up with Verdi HW SW Debug
In this webinar, we will show how simultaneous, synchronized views of design behavior at the software and hardware levels helps engineers at both levels debug efficiently and effectively.
Vaishnav Gorur, Product Marketing Manager, Synopsys, Inc. Alex Wakefield, Engineer, Synopsys, Inc.
Jun 15, 2016

DDR4 for Enterprise Applications
Learn best practices that designers should follow for systems-on-chips (SoCs) connecting to DDR4 in their enterprise applications.
Marc Greenberg, Director of Product Marketing, Synopsys
Jun 02, 2016

SpyGlass New Feature Update (Japanese)
Learn about the latest key feature updates for the SpyGlass version 5.5.0 and 5.6.0 family of products including SpyGlass Lint, SpyGlass CDC, SpyGlass Constraints, SpyGlass Power, and SpyGlass DFT.
Kenichi Komiya, Verification CAE, Synopsys
Jun 01, 2016

Synopsys and ARM Experts Review Smart Constraint Management Practices for Efficient Timing Closure (Simplified Chinese)
Join Synopsys and ARM to learn more about accelerating timing closure by implementing timing constraint best practices.
James Chuang, Technical Marketing Manager, Synopsys
May 26, 2016

Synopsys and ARM Experts Review Smart Constraint Management Practices for Efficient Timing Closure (Traditional Chinese)
Join Synopsys and ARM to learn more about accelerating timing closure by implementing timing constraint best practices.
James Chuang, Technical Marketing Manager, Synopsys
May 26, 2016

Synopsys and ARM Experts Review Smart Constraint Management Practices for Efficient Timing Closure
Join Synopsys and ARM to learn more about accelerating timing closure by implementing timing constraint best practices.
Ramnath Swamy , Principal Engineer, ARM Ayhan Mutlu, Principal Engineer, Synopsys
May 25, 2016

SpyGlass RDC: Solving Design Respins due to Reset Domain Crossings
In this webinar, we will discuss how SpyGlass RDC delivers a unique solution to address RDC issues early at RTL, saving valuable time and costly design re-spins. SpyGlass RDC leverages the industry leading SpyGlass Platform and GuideWare methodology for an easy to use and comprehensive flow for RTL signoff.
Sean O’Donohue, Senior Corporate Application Engineer (CAE), Verification Group; Deep Shah, Senior Corporate Application Engineer (CAE), Verification Group; and Kiran Vittal, Director Product Marketing, Verification Group, Synopsys
May 24, 2016




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