DesignWare IP
Addressing the Challenges of Multi-Protocol High Speed PHY IP in SoC Design
This webinar describes the design challenges and potential advantages of using a multi-protocol 12.5 Gbps PHY that supports a wide range of data rates, features and specifications.
Rita Horner, Product Marketing Manager, Synopsys; Paul Hua, R&D Manager, Synopsys
May 15, 2014

Optimizing DSP cores for Performance and Power with DesignWare Logic Libraries and Embedded Memories
Learn how optimized embedded memories & logic libraries enable your DSP design to achieve performance/power/area targets, and how choosing the correct IP/methodology avoids physical design bottlenecks.
Ken Brock, Product Marketing Manager, Logic Libraries, Synopsys;Ran Snir, VLSI Director, CEVA
Apr 24, 2014

Enrich the Multimedia Experience with HDMI 2.0 (Mandarin)
Learn about the new HDMI 2.0 specification and how it changes the landscape for multimedia SoCs and devices. Get an overview of Synopsys' HDMI 2.0 IP solution and the implementation choices available.
Tina Hu, Interface IP FAE, Synopsys
Apr 15, 2014

Case Study: Application-Specific Processors (ASIP) for the Design of Wireless SoCs
In this webinar we will use several real-world examples to highlight why ASIPs can offer computational performance close to fixed-function hardware blocks, providing instruction-level and data-level parallelism, as well as by introducing specialized hardware operators.
Markus Willems, Product Marketing Manager, Synopsys
Apr 15, 2014

The Top 5 Features to Consider when Choosing a Platform for SoC Software Development
A complete, standalone platform with all the hardware and software needed for software development, debugging, and profiling will significantly accelerate code development for SoC designs.
Allen Watson, Product Marketing Manager for ARC Development Tools, Systems and Ecosystem, Synopsys
Apr 08, 2014

Reducing Power Consumption in Mobile Applications with High-Speed Gear3 MIPI M-PHY IP (Mandarin)
This webinar provides an overview of the MIPI M-PHY and explains the integration challenges faced by designers while integrating M-PHY-based protocols into SoCs for Mobile Multimedia applications.
Haopeng Liu, FAE Manager, Synopsys
Mar 25, 2014

Enrich the Multimedia Experience with HDMI 2.0
Learn about the new HDMI 2.0 specification and how it offers consumers the ultimate home theater experience. This webinar describes the HDMI 2.0 specification, compares it to previous version, and details its new audio, video, and security features.
Manmeet Walia, Senior Product Marketing Manager for DesignWare HDMI IP, Synopsys
Jan 30, 2014

Reducing Power Consumption in Mobile Applications with High-Speed Gear 3 MIPI M-PHY IP
This webinar provides an overview of the MIPI M-PHY and explains the integration challenges faced by designers while integrating M-PHY-based protocols into SoCs.
Hezi Saar, Product Marketing Manager for DesignWare MIPI IP, Synopsys
Jan 22, 2014

Scaling ADC Architectures for Mobile & Multimedia SoCs at 28-nm & Beyond (Mandarin)
Learn about the main analog-to-digital converter (ADC) architectures, how the Successive-Approximation Register (SAR)-based ADC architecture is ideal for ADC implementation in 28nm process nodes and beyond and how it exploits the high speed and high processing power offered by these advanced process technologies.
Ming Han, FAE for Analog IP, Synopsys
Jan 14, 2014

Putting the Smarts into Smart Things - Designing ICs for the Internet of Things
Learn about the trends and challenges designers face when designing next-generation MCUs, and the latest Synopsys design and implementation tool technologies with proven DesignWare IP solutions.
Andy Biddle, Solutions Marketing Manager, Synopsys
Dec 17, 2013

Optimizing High-End Embedded Designs with High-Performance Processors
Learn about the new DesignWare ARC HS Family of high-end embedded processors and how the processors can be quickly optimized to maximize performance and minimize power.
Mike Thompson, Sr. Product Marketing Manager, Synopsys
Dec 12, 2013

Enterprise Ethernet IP for Data Center SoC Designs
The Ethernet protocol is evolving to support faster speeds, lower power and smaller area. This webinar reviews the drivers behind the evolution and how DesignWare 40G Ethernet IP meets these demands.
John Swanson, Product Line Manager, DesignWare Ethernet IP, Synopsys
Dec 05, 2013

Reduce SoC Test Cost and Cut Weeks off Test Integration with Hierarchical Testing of all IP on a SoC
In this webinar we will describe how the DesignWare STAR Hierarchical System leverages IP and logic block-level test and accelerates SoC testing by enabling faster design closure.
Sandeep Kaushik, Sr. Product Manager, Synopsys
Dec 03, 2013

How IP Enables a New Class of SoCs for Data Center Designs
Learn about the latest trends in data center applications such software defined networks and low-power micro servers, and how IP helps address latency, power and RAS requirements for these SoCs.
Ron DiGiuseppe, Senior Strategic Marketing Manager, Synopsys
Sep 19, 2013

Scaling ADC Architectures for Mobile & Multimedia SoCs at 28-nm & Beyond
Learn about the main analog-to-digital converter (ADC) architectures, how the Successive-Approximation Register (SAR)-based ADC architecture is ideal for ADC implementation in 28nm process nodes and beyond and how it exploits the high speed and high processing power offered by these advanced process technologies.
Carlos Azeredo-Leme, Senior Staff Engineer, DesignWare Analog IP, Synopsys
Sep 10, 2013

Simplifying Sensor SoC Integration with a Pre-Verified Sensor IP Subsystem
Learn how an integrated, pre-verified sensor IP subsystem consisting of hardware and software eases the integration effort, while offering a 40-60% area savings with lower latency.
Rich Collins, Product Marketing Manager, IP Subsystems, Synopsys
Sep 04, 2013

M-PCIe: Utilizing Low-Power PCI Express in Mobile Designs
This webinar describes the M-PCIe ECN and its application space, bandwidth and clocking considerations, the PHY interface, power management, and decisions related to the link-layer changes.
Scott Knowlton, Product Marketing Manager, Sr. Staff, DesignWare PCI Express, PCI-X, PCI and SATA IP, Synopsys; Richard Solomon, Technical Marketing Manager, DesignWare PCI Express Controller IP, Synopsys
Aug 27, 2013

3 Easy Ways to Accelerate Development of your Embedded SoC
In this webinar we will show you 3 easy ways to accelerate development time for your embedded SoC software with the DesignWare ARC EM Starter Kit.
Paul Garden, Product Marketing Manager, Synopsys
May 14, 2013

Achieving Predictable and Highly Reliable 10G Backplane Designs
This webinar explores the challenges of implementing 10G backplane systems. The webinar walks through a case study and explores techniques that help designers meet stringent backplane requirements.
David Rennie, Senior Analog Design Engineer for Mixed-Signal Interface IP, Synopsys
May 09, 2013

Implementing Ethernet QoS for use in Automotive Networking Designs
Learn about Ethernet in automotive designs, Audio Video Bridging (AVB), the driving forces and predictions for Ethernet in the automotive market, and Synopsys’ DesignWare Ethernet QoS IP solution.
John Swanson, Product Line Manager, DesignWare Ethernet IP, Synopsys
May 01, 2013

What, Where, Who? Integrating Audio Analog Functionality into SoCs (Mandarin)
Learn what performance trends to consider, where in the system to integrate audio, what challenges are associated with integrating audio in advanced nodes and who to consider in a make vs buy decision.
Ben U, Senior Manager of Analog Design, Synopsys
Apr 10, 2013

Logic Libraries for High-Performance, Processor-Based, Energy-Efficient SoCs
Learn about ways to maximize system performance while managing power budgets of CPU, GPU, and other SoC blocks, each with different performance/power/area targets.
Ken Brock, Product Marketing Manager, Logic Libraries, Synopsys
Apr 02, 2013

Designing with FinFETs
Learn about the benefits and challenges of transitioning from planar to FinFET technologies and their implications for IP design.
Jamil Kawa, Group Director, Solutions Group, Synopsys
Mar 14, 2013

Designing to the New PCI Express 3.0 Equalization Requirements
Designers using PCI Express 3.0 should attend this technical webinar to understand the new Tx and Rx equalization enhancements such as CTLE and DFE, necessary for optimal interconnect performance.
Rita Horner, Senior Technical Marketing Manager for Analog/Mixed Signal IP, Synopsys; David Rennie, Senior Analog Design Engineer for Mixed-Signal Interface IP, Synopsys
Jan 24, 2013

ARC Processors for Linux: Embedded Linux has a New Kid in Town
Learn how Synopsys optimized its DesignWare® ARC™ processor to run Linux and what open source tools and software are available to support the processor.
Allen Watson, Product Marketing Manager for DesignWare ARC Tools, OS and Ecosystem, Synopsys
Jan 15, 2013

Demystifying DDR4 SDRAM for Embedded Applications
Learn about the major features of DDR4 SDRAM as they apply to embedded applications, including key areas for SoC designers to note to take advantage of DDR4’s enhancements over previous generations.
Graham Allan, Senior Product Marketing Manager for Memory Interface IP, Synopsys
Nov 13, 2012

A Large Capacity SRAM Alternative to Embedded DRAM (Mandarin)
Learn how combining innovative power management schemes with TSMC certified bitcells delivers a compelling alternative to embedded DRAM.
Feng Li, FAE, Synopsys, Inc.
Oct 25, 2012

What, Where, Who? Integrating Audio Analog Functionality into SoCs
Learn what performance trends to consider, where in the system to integrate audio, what challenges are associated with integrating audio in advanced nodes and who to consider in a make vs buy decisions.
Craig Zajac, Senior Product Marketing Manager, Synopsys
Sep 25, 2012

Achieve Lower Silicon Cost Using Embedded Memory Test and Repair
Learn about the technical trends and challenges associated with embedded test, repair and diagnostics in today’s designs and how Synopsys’ STAR Memory System® addresses these challenges.
Yervant Zorian, Chief Architect for embedded test & repair products, Synopsys
Sep 19, 2012

Optimizing Power in High-Performance SoCs using Multiple Voltage/VT/Channel Length Libraries
Learn ways to maximize system performance and minimize cost while slashing power budgets of SoC blocks operating at different clock speeds.
Ken Brock, Product Marketing Manager, Synopsys
Aug 02, 2012

A Large Capacity SRAM Alternative to Embedded DRAM
Learn how combining innovative power management schemes with TSMC certified bitcells delivers a compelling alternative to embedded DRAM.
Prasad Saggurti, Product Marketing Manager, Synopsys
Jul 19, 2012

Chinese Version: Audio IP Subsystems Made Easy with a Complete, SoC-Ready Solution
Learn how dedicated audio subsystems can offload the audio processing from the host processor, thus reducing design complexity and improving performance and efficiency of SoCs.
Chris Wu, Staff FAE, Synopsys
Jun 28, 2012

Reduce Mobile Device Costs and Board Area with MIPI Low Latency Interface (LLI) and M-PHY
Learn how the MIPI Alliance Low Latency Interface (LLI) and M-PHY can help future-proof a mobile device design while giving it an advantage in cost, board space, performance, and time-to-market.
Hezi Saar, Staff Product Marketing Manager, Synopsys; Kurt Schuler, VP of Marketing, Arteris; Philippe Martin; Vice President, Corporate Applications, Arteris
Jun 27, 2012

Chinese Version: ARC Android - Making Android Affordable Anywhere
Learn about the ARC processor architecture in the DesignWare ARC Android solution which enables performance optimizations for the most power and cost sensitive market segments.
Chris Wu, Staff FAE, Synopsys
May 09, 2012

Audio IP Subsystems Made Easy with a Complete, SoC-Ready Solution
Learn how dedicated audio subsystems can offload the audio processing from the host processor, thus reducing design complexity and improving performance and efficiency of SoCs.
Henk Hamoen, Senior Product Marketing Manager, Synopsys
Apr 26, 2012

Effect of Jitter on Data Converters
Learn about the frequency domain mechanisms that relate jitter to sampling errors which enables designers to handle the design trade-offs and to achieve optimal system and data converter performance.
Carlos Azeredo-Leme, Senior Staff Engineer for the DesignWare Analog IP, Synopsys
Apr 24, 2012

Bringing Embedded MTP NVM IP to Advanced Process Nodes
Learn how Synopsys aligns application/market needs to provide embedded multiple time programmable (MTP) non-volatile memory (NVM) IP at advanced nodes with optimized, targeted technology capabilities
Craig Zajac, Senior Product Marketing Manager, Synopsys
Apr 12, 2012

ARC Android - Making Android Affordable Anywhere
Learn about the ARC processor architecture in the DesignWare ARC Android solution which enables performance optimizations for the most power and cost sensitive market segments.
Chris Caerts, Product Marketing Manager, Synopsys, Inc.
Jan 18, 2012

Reliability and Qualification of MTP NVM IP from Commercial to Automotive Applications
How Synopsys designs and executes on a silicon testing methodology for embedded MTP NVM IP technology, enabling SoC designers with reliable and qualified solutions for their end applications
Ting-Jia Hu, Sr. Program Manager for DesignWare NVM IP, Synopsys
Jan 10, 2012

Introducing the DesignWare ARC EM 32-bit Processor Family for Embedded Applications
Learn how the new ARC EM processor family enables development of advanced processors with optimum balance of performance, power and area; performance exceeding 1.5 DMPS/MHz; and power-efficiency of less than 2uW/DMIPS at 28-nm.
Steve Tateosian, Product Marketing Manager ARC Processors, Synopsys
Oct 25, 2011

Chinese Version: Introducing the DesignWare ARC EM 32-bit Processor Family for Embedded Applications
Learn how the new ARC EM processor family enables development of advanced processors with optimum balance of performance, power and area.
Chris Wu, Staff FAE, Synopsys
Oct 25, 2011

Addressing the Challenges of Designing an AMBA(R)-based SoC with a PCI Express(R) Interface
The Webinar will explore trade-offs and implementation issues through lessons learned from the development of Synopsys DesignWare IP for PCI Express solutions and the customers that have used them.
Frank Kavanagh, Senior Engineering Manager, DesignWare Digital Controllers for PCI Express, Synopsys
Oct 20, 2011

Chinese Version: Build Low-power, high-performance mobile SoCs with complete MIPI solutions
Learn about the building blocks and integration challenges faced by SoC designers integrating MIPI protocols to interface to camera, display, RFIC, storage and chip to chip connectivity.
Haopeng Liu, FAE, Synopsys
Oct 17, 2011

Reliability and Qualification of MTP NVM IP from Commercial to Automotive Applications
How Synopsys designs and executes on a silicon testing methodology for embedded MTP NVM IP technology, enabling SoC designers with reliable and qualified solutions for their end applications.
Martin Niset, Senior Product and Test Engineering Manager, Synopsys
Oct 05, 2011

Embedded Memory Test and Repair Solution: Keeping Up with Changing Design Applications and Shrinking Process Technologies
This webinar discusses key points of interest for implementing embedded memory test, repair and diagnostics solution in today's designs.
Yervant Zorian, Chief Architect, Synopsys; Sandeep Kaushik, Product Marketing Manager, Synopsys
Sep 13, 2011

Build low–power, high-performance mobile SoCs with complete MIPI solutions
Learn about the building blocks and integration challenges faced by SoC designers integrating MIPI protocols to interface to camera, display, RFIC, storage and chip to chip connectivity.
Hezi Saar, Product Marketing Manager, Synopsys
Jul 26, 2011

Building High-Performance SoCs with Configurable and Extensible Processors
Learn how the configurable, extensible DesignWare® ARC™ 32-bit processors offers a broad range of features that enable you to tailor the core for your specific embedded or host application.
Mike Thompson, Sr. Product Marketing Manager, Synopsys
Apr 07, 2011

HDMI: Enabling the 3D Revolution
This webinar discusses the latest trends in HDMI and how advanced features address the challenges of implementing 3D capabilities in SoC design.
Manmeet Walia, Senior Product Manager, Mixed-Signal PHY IP, Synopsys
Mar 31, 2011

Implementing an Embedded Memory Subsystem in Mobile Applications
Learn how to minimize low-power design complexity for your mobile SoC applications with embedded memory IP that is optimized for power, performance and density.
Prasad Saggurti, Product Marketing Manager, Synopsys
Mar 29, 2011

Using IP-XACT to Streamline SoC Design and Verification
The IEEE IP-XACT specification is a valuable format that can help solve IP integration challenges when combined with quality tools designed for an IP-based design and verification flow.
John A. Swanson, Senior Manager, Synopsys
Mar 17, 2011

DesignWare IP for AMBA 3 AXI On-Chip Bus
This webinar details the flexible on-chip bus architecture of the DesignWare interconnect fabric that enables dedicated high-performance and shared low-performance links to be combined within a single AMBA 3 AXI on-chip interconnect, eliminating unnecessary logic within the design to deliver maximum bandwidth while reducing area, routing congestion and power.
Fred Roberts, Corporate Applications Engineer, Synopsys
Feb 10, 2010



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