|How Reliable is Your FPGA Design? Tips and Tricks for Building-in High Reliability|
Learn how to automatically "build in" high reliability using Synopsys Synplify Premier FPGA design tool.
Sharath Duraiswami, Senior Corporate Applications Engineer, Synopsys
Oct 02, 2014
|Automate ASIC to FPGA-based Prototype Conversion with Synplify|
Using Synplify, automate ASIC to FPGA-based prototype conversion to accelerate fast FPGA-based working prototype bring-up, debug and validation.
Dr. Angela Sutton, Staff Product Marketing Manager, FPGA Implementation, Synopsys
Jun 18, 2014
|Increase FPGA Performance with Enhanced Capabilities of Synplify Pro and Premier|
Timing is everything! Find out how to reproducibly improve FPGA performance results using Synplify Pro and Synplify Premier. This webinar includes tips on how to set up you FPGA design to achieve better timing results downstream, recommended techniques to analyze and tune design performance for faster timing closure and new "under the hood" Synplify Premier placement-aware logic synthesis technology that further boosts timing performance.
Paul Owens, Senior CAE, Synplify Business Group, Synopsys
May 06, 2014
|Using FPGA-based Prototyping to Validate IP Integration Without Breaking a Sweat|
Learn how to test DesignWare USB 3.0 interface IP and implement it on a HAPS FPGA-based Prototyping System. Review best practices on how to utilize Synopsys' Identify HW/SW tools to test the interface in the context of the larger chip design.
John Kuhns, Synopsys Professional Services, Senior Design Consultant
Jul 17, 2013