FPGA
How Flexible Debug Can Speed Physical Prototype Bring-Up and Software Development
This webinar will provide an overview of the wide spectrum of critical debug techniques for efficient FPGA-based prototype bring-up, embedded software development and hardware/software integration.
Achim Nohl, Technical Marketing Manager, Synopsys
Mar 02, 2016

Building Highly Reliable FPGA Designs for Applications Needing Functional Safety
In this webinar you will learn how to automatically "build in" high reliability using Synopsys Synplify Premier FPGA design tools.
Sharath Duraiswami, Senior Corporate Applications Engineer, Synopsys
Nov 11, 2015

A High Performance and Affordable Way to Validate SoC and ASIC Designs
This webinar will introduce Synopsys' HAPS®-80 Series of FPGA-based prototyping systems, which have been designed to deliver maximum system performance and support for up to 1.6 billion ASIC gates.
Neil Songcuan, Senior Product Marketing Manager, Synopsys
Sep 30, 2015

Getting the Most out of IP-based Designs with Synplify FPGA Design Tools
Learn how to streamline and automate your IP-based FPGA design flow using Synopsys FPGA design tools, allowing you to attain your design objectives within the framework of how IP will be delivered.
Parminder Gill, Engineering Project Leader, FPGA Implementation, Synopsys
Feb 03, 2015

How Reliable is Your FPGA Design? Tips and Tricks for Building-in High Reliability
Learn how to automatically "build in" high reliability using Synopsys Synplify Premier FPGA design tool.
Sharath Duraiswami, Senior Corporate Applications Engineer, Synopsys
Oct 02, 2014

Automate ASIC to FPGA-based Prototype Conversion with Synplify
Using Synplify, automate ASIC to FPGA-based prototype conversion to accelerate fast FPGA-based working prototype bring-up, debug and validation.
Dr. Angela Sutton, Staff Product Marketing Manager, FPGA Implementation, Synopsys
Jun 18, 2014

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro and Premier
Timing is everything! Find out how to reproducibly improve FPGA performance results using Synplify Pro and Synplify Premier. This webinar includes tips on how to set up you FPGA design to achieve better timing results downstream, recommended techniques to analyze and tune design performance for faster timing closure and new "under the hood" Synplify Premier placement-aware logic synthesis technology that further boosts timing performance.
Paul Owens, Senior CAE, Synplify Business Group, Synopsys
May 06, 2014