|How Reliable is Your FPGA Design? Tips and Tricks for Building-in High Reliability|
Learn how to automatically "build in" high reliability using Synopsys Synplify Premier FPGA design tool.
Sharath Duraiswami, Senior Corporate Applications Engineer, Synopsys
Oct 02, 2014
|Automate ASIC to FPGA-based Prototype Conversion with Synplify|
Using Synplify, automate ASIC to FPGA-based prototype conversion to accelerate fast FPGA-based working prototype bring-up, debug and validation.
Dr. Angela Sutton, Staff Product Marketing Manager, FPGA Implementation, Synopsys
Jun 18, 2014
|Increase FPGA Performance with Enhanced Capabilities of Synplify Pro and Premier|
Timing is everything! Find out how to reproducibly improve FPGA performance results using Synplify Pro and Synplify Premier. This webinar includes tips on how to set up you FPGA design to achieve better timing results downstream, recommended techniques to analyze and tune design performance for faster timing closure and new "under the hood" Synplify Premier placement-aware logic synthesis technology that further boosts timing performance.
Paul Owens, Senior CAE, Synplify Business Group, Synopsys
May 06, 2014
|Using FPGA-based Prototyping to Validate IP Integration Without Breaking a Sweat|
Learn how to test DesignWare USB 3.0 interface IP and implement it on a HAPS FPGA-based Prototyping System. Review best practices on how to utilize Synopsys' Identify HW/SW tools to test the interface in the context of the larger chip design.
John Kuhns, Synopsys Professional Services, Senior Design Consultant
Jul 17, 2013
|High-Throughput FPGA Signal Processing: Trends, Tips & Tricks for QoR and Design Reuse|
Learn about best practices for creating high-throughput signal processing designs for FPGAs, with a focus on achieving quality of results and design reuse across FPGA devices, families, and vendors.
Chris Eddington, Sr. Technical Marketing Manager, Synopsys
Jul 09, 2013
|10 ways to Debug your FPGA Design|
Learn how to cut FPGA debug time with more effective diagnosis of FPGA design setup and design specifications, and by identifying design errors en-masse in a single iteration. If you are an ASIC designer, learn techniques to more quickly make your design "FPGA friendly" to get working FPGA implementation on the board.
Angela Sutton, Staff Product Marketing Manager, FPGA Implementation , Synopsys, Inc.
Feb 12, 2013
|Debugging Methods for FPGA-Based Prototypes - Best Practices for System Troubleshooting and RTL Debug|
Learn about new methods and technology to increase the ROI of an FPGA-based prototype and expand its role for hardware/software validation.
Troy Scott, Product Marketing Manager, Synopsys
Sep 18, 2012
|Faster, Safer Implementation of High-Reliability, High Availability Designs using FPGAs|
Learn techniques on how to build high operation reliability into your FPGA designs in the face of radiation-induced errors in the field, and how to validate and trace the result of your design implementation before you deploy your FPGA-based system.
Angela Sutton, Staff Product Marketing Manager, FPGA Implementation
Jul 14, 2011