In-Design
Samsung and Synopsys 14nm Physical Verification in IC Validator and In-Design with IC Compiler II
Samsung and Synopsys together present a webinar on the manufacturing and physical verification challenges and solutions at 14nm.
KK, Lin, Director of Foundry Design, Samsung; Jonathan White, CAE Directory, Synopsys, Inc.
Jun 28, 2016

TSMC and Synopsys: 10nm Physical Verification Enablement for IC Validator
Learn about TSMC’s 10nm design enablement readiness & the tooling supported in their physical design flow; Synopsys will cover new technologies addressing the challenges of 10nm design verification.
Captain Liu, Manager, Design Methodology and Service Marketing TSMC; Ron Duncan, Sr. CAE Manager, Synopsys
Mar 03, 2016



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