Low Power
Identifying and Resolving Low Power Issues Before Tapeout
This webinar highlights how to find low power issues during verification using Formality.
Bob Hatt, Staff Corporate Applications Engineer, Synopsys
Sep 29, 2015

An Approach for Efficient IP Reuse in a Hierarchical UPF Methodology
This webinar will help you understand a Liberty-based approach for effective IP reuse in implementation of a multi-voltage hierarchical design using the IEEE 1801 (UPF) standard.
Viswanath K. Ramanathan, Corporate Applications Engineer, Synopsys; Mary Ann White, Director of Product Marketing, Synopsys
Feb 26, 2015

Imagination and Synopsys: Reduce Dynamic Power and Area up to 50% on a GHz+ MIPS Core Implementation
In this webinar, Imagination Technologies will share how their selection of standard cell architecture and use of several dynamic power techniques available in Design Compiler and IC Compiler helped them achieve optimal power and area savings for their MIPS family of CPU cores.
Maya Mohan, Hardware Design Engineer, Imagination Technologies and Jeffrey Lee, CAE Manager, Power Compiler, Synopsys
Jul 10, 2014

Using a Golden UPF Methodology for Low Power Designs
This webinar will help you understand the best practices for implementation of a Golden UPF flow for Multi-Voltage designs using the IEEE 1801 (UPF) standard.
Somil Ingle, Sr. Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Apr 03, 2014