Low Power
An Approach for Efficient IP Reuse in a Hierarchical UPF Methodology
This webinar will help you understand a Liberty-based approach for effective IP reuse in implementation of a multi-voltage hierarchical design using the IEEE 1801 (UPF) standard.
Viswanath K. Ramanathan, Corporate Applications Engineer, Synopsys; Mary Ann White, Director of Product Marketing, Synopsys
Feb 26, 2015

Imagination and Synopsys: Reduce Dynamic Power and Area up to 50% on a GHz+ MIPS Core Implementation
In this webinar, Imagination Technologies will share how their selection of standard cell architecture and use of several dynamic power techniques available in Design Compiler and IC Compiler helped them achieve optimal power and area savings for their MIPS family of CPU cores.
Maya Mohan, Hardware Design Engineer, Imagination Technologies and Jeffrey Lee, CAE Manager, Power Compiler, Synopsys
Jul 10, 2014

Using a Golden UPF Methodology for Low Power Designs
This webinar will help you understand the best practices for implementation of a Golden UPF flow for Multi-Voltage designs using the IEEE 1801 (UPF) standard.
Somil Ingle, Sr. Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Apr 03, 2014

A Hierarchical, Low Power Design Approach for Gigascale Designs
This webinar will help you understand the best practices for implementation of a Multi-Voltage hierarchical design using the IEEE 1801 (UPF) standard.
Viswanath K. Ramanathan, Corporate Applications Engineer, Synopsys; Mary Ann White, Director of Product Marketing, Synopsys
Apr 24, 2013

Static Verification of Advanced Low Power Designs
Learn about advanced low power techniques and the static checking capabilities designers need to verify the consistency and correctness of low power intent and implementation through the flow.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Vinay Srinivas, R&D Group Director, Low Power Verification, Synopsys; Prapanna Tiwari , CAE Manager, Low Power Verification, Synopsys
Oct 30, 2012

Low Power Designs Made Easy: Create, Visualize and Debug Your Power Intent
This webinar will show you the various steps to easily generate, view, refine and debug the power intent of your design, as specified with the IEEE 1801 (UPF) format. You will learn effective techniques to speed up the implementation of your advanced low power designs. This webinar will be valuable for both new and experienced users of power intent. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.
Sebastian Brugnoli, Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Mar 07, 2012

Reduce Power Consumption 30% with Advanced Synthesis Techniques
In this webinar you will learn how new advances in clock gating and voltage threshold (Vt) optimization available in Design Compiler can reduce your dynamic and leakage power by 10-30%. An interactive Q&A session follows the technical presentation.
Mary Ann White, Product Marketing Director, Synopsys; Rishi Chawla, Sr. Application Engineering Manager, Synopsys
Apr 14, 2011