|Putting the Smarts into Smart Things - Designing ICs for the Internet of Things|
Learn about the trends and challenges designers face when designing next-generation MCUs, and the latest Synopsys design and implementation tool technologies with proven DesignWare IP solutions.
Andy Biddle, Solutions Marketing Manager, Synopsys
Dec 17, 2013
|A Hierarchical, Low Power Design Approach for Gigascale Designs|
This webinar will help you understand the best practices for implementation of a Multi-Voltage hierarchical design using the IEEE 1801 (UPF) standard.
Viswanath K. Ramanathan, Corporate Applications Engineer, Synopsys; Mary Ann White, Director of Product Marketing, Synopsys
Apr 24, 2013
|Verifying Advanced Low Power Designs: Find Design-Killing LP Bugs Early and Easily|
Learn how VCS with MVSIM Native Low Power provide the accuracy and comprehensive LP support needed at RTL, and enable LP bugs to be found and fixed early and easily in the design cycle.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Aditya Kher, Senior Corporate Application Engineer (CAE), Low Power Verification, Synopsys; Harsh Chilwal, Senior R&D Engineer, Synopsys
Apr 04, 2013
|Static Verification of Advanced Low Power Designs|
Learn about advanced low power techniques and the static checking capabilities designers need to verify the consistency and correctness of low power intent and implementation through the flow.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Vinay Srinivas, R&D Group Director, Low Power Verification, Synopsys; Prapanna Tiwari , CAE Manager, Low Power Verification, Synopsys
Oct 30, 2012
|New Features and Methodologies for Simplifying Hierarchical Low Power Verification with Formality|
This webinar will discuss new features in Formality to help make low power hierarchical verification easer. We will also cover how to write your power intent (UPF) to help you implement a robust, simplified, hierarchical verification flow.
Bob Hatt, Corporate Applications Engineer, Synopsys
Oct 10, 2012
|Accurate Early Stage Power Estimation with PrimeTime PX: The NVIDIA Experience|
In this webinar we will review the need for early power analysis, and show how useful power estimates can be achieved even with early and/or incomplete data. NVIDIA will outline their strategies.
Miodrag Vujkovic, Senior ASIC Design Engineer, NVIDIA; Maria Tovey, Corporate Applications Engineer, Synopsys
Oct 04, 2012
|5X Faster PrimeTime Multivoltage Timing Signoff: A Renesas Case Study|
Learn how PrimeTime’s new multivoltage aware analysis technology reduces risk and speeds signoff for designs with multiple voltage domains, and how Renesas has successfully deployed it to reduce signoff turnaround time by 5X.
Francis Cheung, Senior Staff Engineer, EDA Engineering, Engineering Unit , Renesas Electronics America, Inc.; Carol Scemanenco, Senior Staff Engineer, Implementation R&D Group, Synopsys, Inc.
Jul 31, 2012
|Low Power Designs Made Easy: Create, Visualize and Debug Your Power Intent|
This webinar will show you the various steps to easily generate, view, refine and debug the power intent of your design, as specified with the IEEE 1801 (UPF) format. You will learn effective techniques to speed up the implementation of your advanced low power designs. This webinar will be valuable for both new and experienced users of power intent. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.
Sebastian Brugnoli, Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Mar 07, 2012
|Lighter, Easier and More Flexible Approaches for Multi-Voltage Low Power Design Specification|
In this webinar you will learn how various ways of describing power intent with IEEE 1801 (UPF) can help you achieve more efficient low power designs. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.
Somil Ingle, Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Oct 12, 2011
|Reduce Power Consumption 30% with Advanced Synthesis Techniques|
In this webinar you will learn how new advances in clock gating and voltage threshold (Vt) optimization available in Design Compiler can reduce your dynamic and leakage power by 10-30%. An interactive Q&A session follows the technical presentation.
Mary Ann White, Product Marketing Director, Synopsys; Rishi Chawla, Sr. Application Engineering Manager, Synopsys
Apr 14, 2011