|Achieving Faster Design Closure on Imagination Technologies' GPU Core using Lynx Design System|
Learn how to achieve faster design closure for a complex graphics core using Synopsys’ Lynx technology plug-in for Imagination Technologies' PowerVR Series6 GPU core by leveraging the exploration and feasibility analysis capabilities of Synopsys Design Compiler and IC Compiler.
Chad Gamble, Lynx Design System CAE, Synopsys
Oct 09, 2013
|Late-Stage Leakage Recovery using the Lynx Design System|
The rate of increase in SoC design complexity continues to challenge even the most experienced design teams. Synopsys’ Lynx Design System can help manage many of these complexities. This webinar will discuss strategies that leverage Final Stage Leakage-Power Recovery (FSLR) in IC Compiler, the new PrimeTime ECO Leakage flow and multi-channel libraries to recover leakage power late in the design cycle. These methodologies, as a part of a complete RTL-to-GDSII design solution available in Lynx, can help you achieve your power targets while maintaining design performance. These capabilities will be shown live in a short demo.
Devin Bright, Synopsys
May 08, 2013
|Proven Techniques for Hierarchical Design Complexity using Lynx (Simplified Chinese)|
You will learn about advanced f techniques within Synopsys' IC Compiler and Lynx Design System to manage hierarchical design complexity.
Ziyu Wu, Corporate Application Engineer, Lynx Design System, Synopsys
Jan 21, 2013
|Proven Techniques for Hierarchical Design Complexity using Lynx|
In this webinar, you will learn about advanced flows and techniques available with Synopsys' IC Compiler and Lynx Design System to manage hierarchical design complexity.
Lydia Lee, Application Engineer, Synopsys Inc.
Sep 26, 2012
|Faster Timing Closure with the Lynx Design System|
Using the Lynx Design System, you will learn how to leverage the advanced timing closure features available with Synopsys’ IC Compiler and PrimeTime.
Aditya Ramachandran, Lynx CAE, Synopsys
May 09, 2012
|Managing Hierarchical, Low Power Design Challenges with the Lynx Design System|
In this seminar, we will demonstrate silicon-proven methodologies to describe power intent with IEEE 1801 (UPF) using a hierarchical design flow to address power consumption and design size concurrently. We will walk you through some of the key steps in implementing and analyzing a hierarchical design using UPF for both bottom-up and top-down Synopsys Galaxy-based flows.
Chad Gamble, Synopsys
Jan 17, 2012
|Optimize in Less Time: Rapid Design Exploration with Lynx Design System|
Every SoC design requires a unique implementation strategy to navigate the tradeoffs between power, performance and area to achieve the best results for the specific use.
Aditya Ramachandran, CAE, Lynx Design System, Synopsys
Jul 19, 2011