| Samsung Foundry and Synopsys Discuss Enabling 14-nm FinFET Design | Samsung Foundry and Synopsys present the challenges and opportunities of manufacturing with Samsung's 14-nm FinFET process and how these changes impact design enablement.
Dr. Kuang-Kuo Lin, Director, Foundry Design Enablement, Samsung Semiconductor Inc. (SSI); Dr. Henry Sheng, Senior Director of R&D, Synopsys
May 28, 2013 |
| | Recover Leakage and Maintain Signoff Timing – with Customer Case Studies | This webinar will introduce PrimeTime ECO technology designed to recover leakage power, without introducing timing violations. We’ll share customer data that shows leakage power recovery up to 40%.
Rupesh Nayak, R&D Manager, Synopsys; Sasan Absalan, Corporate Applications Engineer, Synopsys
Jan 29, 2013 |
| | Accelerate Design Closure with PrimeRail In-Design Rail Analysis | Hear how to use PrimeRail’s In-Design Rail Analysis within IC Compiler to help you identify problems early in the design cycle and achieve faster design closure.
Jason Binney, Priciple CAE, Synopsys
Jan 23, 2013 |
| | Samsung and Synopsys Share Multicorner-Multimode Perspectives | This webinar highlights strategies for dealing with the large number of scenarios in the physical implementation flow. Samsung Semiconductor Inc. shares their experience using the IC Compiler- based MCMM solution to successfully meet their aggressive design objectives and Synopsys shares its multicorner-multimode (MCMM) design solution for addressing variability and design complexity at advanced technology nodes.
Santhosh Pillai, Senior Engineering Manager, Samsung, San Jose (SSI); Thomas Andersen, Director of R&D, IC Compiler, Synopsys
Oct 31, 2012 |
| | Accelerate Time-to-Tapeout with IC Compiler Custom Co-Design | Learn how using IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development.
Christopher Shaw, Senior Staff Technical Marketing Manager, Synopsys; Randy Bishop, Principal Engineer, Synopsys
Oct 24, 2012 |
| | Enabling 20nm Design: A Foundry and EDA Perspective | TSMC and Synopsys will jointly present some of the key design and manufacturing challenges at 20nm process technology. They will highlight the need for early collaboration between EDA, customers and the foundry to ensure a smooth path to tape-out and first-time silicon success.
Willy Chen, Department Manager, Design Methodology & Service Marketing Program R&D, TSMC; Dr. Tong Gao, Synopsys Fellow, Synopsys
May 01, 2012 |
| | Efficient Clock Distribution: A Critical Factor in Design Performance | Synopsys and LSI jointly present on designing today’s high frequency, low power clocks. LSI will present their perspective on the challenges of clock distribution and Synopsys will focus on the solutions that enable designers to achieve the best QoR and lowest power at today’s advanced technology nodes.
JC Parker, Senior Director of Design Tools and Methodologies, LSI; Dennis Ding, R&D Director, Synopsys
Apr 04, 2012 |
| | Streamlining Your ECO Flow For Fastest Setup, Hold and Timing DRC Closure | Learn what’s new with timing-aware DRC guidance for ECOs and which design flow and tool settings provide the fastest timing closure at 28 nm and below.
Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys; Vivek Ghante, Staff Corporate Applications Engineer, Implementation Group, Synopsys
Mar 14, 2012 |
| | Use IC Compiler and Custom Designer to Shave Weeks Off Your SoC Development Cycle | Learn how the seamless integration between IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits at any stage of development.
Chris Shaw, Sr. Technical Marketing Manager, Synopsys;
Denis Goinard, CAE Manager, Synopsys
Oct 19, 2011 |
| | Save Weeks Fixing ECOs with PrimeTime and IC Compiler | See how design teams are saving weeks during implementation and signoff. Learn how PrimeTime Next-Generation ECO guidance and IC Compiler automatically fix DRC, setup and hold violations to reduce it.
Troy Epperly, Staff Engineer, CAE, Implementation Group, Synopsys; Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys
Jul 20, 2011 |
| | Optimize in Less Time: Rapid Design Exploration with Lynx Design System | Every SoC design requires a unique implementation strategy to navigate the tradeoffs between power, performance and area to achieve the best results for the specific use.
Aditya Ramachandran, CAE, Lynx Design System, Synopsys
Jul 19, 2011 |
| | Faster ECO Fixing Flows with PrimeTime and IC Compiler | This technical webinar will explain how IC Compiler and PrimeTime can be used to close timing during signoff. It will focus on the use of Distributed Multi-Scenario Analysis for automatic set-up and hold fixing, and will explain new PrimeTime 2010.06 DRC fixing capabilities. Attendees will learn how to minimize fixing run times, which approaches are best for closing setup and hold violations, and how to deploy SI fixing most effectively.
Uyen Tran, Director, CAE, Implementation Group, Synopsys; Jennifer Pyon, Senior Staff Engineer, CAE, Implementation Group, Synopsys
Jul 20, 2010 |
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