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Q&A with Troy Scott on Synopsys Hybrid Protoyping Solution 

The recent announcement of Synopsys’ industry-first integrated hybrid prototyping solution combines Synopsys Virtualizer™ virtual prototyping and Synopsys HAPS® FPGA-based prototyping to accelerate the development of system-on-chip (SoC) hardware and software. We caught up with Troy Scott, senior product marketing manager, FPGA-based prototyping solutions, to gain more insight into the significance of this development for designers and the industry.

Troy Scott

1. What prototyping challenges are being faced by designers today?

Troy: Earlier prototype availability is the top concern for virtual and system prototype developers and those creating FPGA-based hardware prototypes. The sooner a high-performance and realistic prototype is available, the sooner software development can begin. Earlier prototyping remains the key strategy to shorten time-to-market and increase the quality of complex SoC designs. The availability of system-level models and the effort to design new SoC blocks can delay the availability of an SoC prototype. Prototype capacity, debug visibility, and the fidelity and accuracy of models can also constrain the degree of hardware/software validation that can be performed.

2. What is Synopsys’ hybrid prototyping solution?

Troy: Synopsys’ hybrid prototyping solution integrates Synopsys Virtualizer-based virtual prototypes and HAPS FPGA-based prototypes into a single prototyping environment. High performance data exchange is made possible through new AMBA® transactors and Synopsys’ low-latency UMRBus physical link. This gives designers the flexibility to partition the SoC design into virtual and FPGA-based environments at the natural block-level boundaries of the AMBA® interconnect to maximize the overall system performance.

3. How does Synopsys’ hybrid prototyping solution benefit customers?

Troy: Hybrid prototyping enables hardware and software engineers to:
  • Get the best of both worlds by seamlessly linking virtual and FPGA-based prototypes.
  • Partition SoC design blocks between virtual and FPGA-based prototype environments to maximize overall prototype performance.
  • Improve debug visibility and control of software under development through the Virtualizer-based environment of the hybrid prototype.
  • Accelerate system bring-up using virtual prototyping for new design blocks and FPGA-based prototyping for existing logic.
  • Easily integrate high performance ARM® Cortex processor models, transactors for ARM® AMBA® interconnect and Synopsys DesignWare® IP with the rest of the SoC design into a single hybrid prototype.
  • Start software development up to 12 months earlier in the design cycle and speed hardware/software integration and system validation.

4. What makes this an industry first? Aren’t hybrid prototyping solutions already in existence today?

Troy: This is the industry’s first integrated, commercially available solution combining both virtual prototyping and FPGA-based prototyping into a single solution. Synopsys’ offering uniquely combines the accuracy and speed of hardware (Synopsys HAPS) with the flexibility and visibility of a software prototype (Synopsys Virtualizer).

Currently, designers have to develop mostly custom technology to establish communication between virtual and hardware prototypes. Exchanging data between the abstract SystemC models and cycle-accurate hardware through a standard bus protocol requires a deep understanding of the bus transaction protocols as well as clock management and data buffering for system coherency. This knowledge is typically spread across multiple engineers, some of whom are experts in SystemC/C++ and others in creating synthesizable RTL, so applying all the required expertise can be time consuming and prone to error. Because of the benefits of hybrid prototyping, many companies make the investment to connect the prototypes themselves. Synopsys offers a pre-designed, pre-validated hybrid prototyping solution, including the virtual and hardware prototypes as well as both the logical and physical link between the prototypes.

5. How do developers use hybrid prototypes?

Troy: Hybrid prototypes are most commonly used for software development, hardware-software integration and system validation. During the hardware bring-up and firmware driver phases of design the OS configuration and install can be validated along with kernel and user space debugging. Later during application software, QA, and system tests the prototype supports unit and system tests. Since hybrid prototypes are fairly portable and don’t require advanced power and cooling environments they can be also be deployed to the field for diagnostics.

6. How does a hybrid prototype compare to other system verification and validation methods on the market today?

Troy: The main difference is system prototype performance. Since the advent of transaction-level-model (TLM)-based prototypes and standard co-emulation modeling interface (SCE-MI) models, EDA vendors have attempted to create co-emulation links between HDL simulators, ASIC emulators, and SystemC models. These systems provide high hardware debug visibility at the expense of performance. Hybrid prototypes that combine Synopsys-based virtual and FPGA-based prototypes are orders of magnitude faster than co-emulation verification using an ASIC emulator or HDL simulator, delivering performance between 50-200MHz.

7. What are the key components of Synopsys’ hybrid prototype solution?

Troy: Hybrid prototypes combine Synopsys Virtualizer virtual prototyping and HAPS-60 series FPGA-based prototyping products. The data exchange is accomplished through Synopsys’ high-performance Universal Multi-Resource (UMRBus) physical link, which efficiently transfers data between a host workstation running the virtual SystemC/TLM environment and a HAPS-60 motherboard. The HAPS UMRBus Interface Kit product provides the required interface hardware and cabling. The Synopsys transactor libraries support AMBA 2.0 AHB™/APB™, AXI™ 3 AXI 4, and AXI 4 ACE Lite™ interconnects, giving designers the flexibility to efficiently partition the SoC design between the virtual or FPGA-based prototypes. The transactor libraries are distributed as part of the HAPS-60 Co-Sim & Transaction-Based Verification (TBV) Suite. In addition, an API is provided for use with any C++ environment, and a Virtualizer-specific API is provided for SystemC user applications.

8. What is the general feedback that Synopsys is receiving about the new Hybrid Prototyping technology?

Troy: Feedback about the solution has been positive. The Synopsys transactor library can be applied in a variety of usage scenarios. Design teams have identified two popular applications for a hybrid prototype:
  1. Data streaming from a user application running on a host PC to drive the HAPS hardware using AMBA bus protocol interactions. This is a low-effort way to add software-based validation scenarios to a HAPS system. The hybrid prototype in this scenario supports IP validation in a real world environment. The device under test (DUT) is hosted by FPGAs and connected to physical interfaces and potentially other SoC blocks. An AMBA® bus master transactor connects to the slave ports of the DUT and is driven by a user binary executing on the external workstation. The use of AMBA® transactors provides a familiar and abstract way to create a C++-based test bench to drive the physical prototype.
  2. In-context IP validation where a processor subsystem executes IP validation software on the virtual platform to validate IP executing on the HAPS hardware. This scenario involves multiple transactors to connect a virtual processor subsystem to a DUT hosted by FPGAs. AMBA® transactors bridge the virtual loosely timed models with cycle-accurate physical prototype. The virtual platform supports the embedded OS and application test programs can be applied to validate the DUT. A common starting point for this sort of HW/SW validation is to modify a Synopsys VDK (Virtualizer Development Kit) with Synopsys Virtualizer and add or substitute in AMBA® transactors for SoC blocks hosted by a HAPS-60 system.

    9. What are the next steps for this new technology? For the industry?

    Troy: TLM transactors expand the number of hardware/software validation scenarios possible with FPGA-based prototypes. New technology advances will likely offer more protocol variations and other popular on-chip bus types. Performance is always top of mind for designers so throughput latency of the system will remain a focus for future development. From an industry perspective, the expense and effort to validate deep software stacks on new SoC platforms is driving the demand for faster and more capable prototyping platforms. Innovation in virtual and FPGA-based prototypes will help address the need to bring-up and deploy prototypes sooner during SoC development projects.

    To find out more information about the Synopsys Hybrid Prototyping Solution please visit: http://www.synopsys.com/Systems/FPGABasedPrototyping/Pages/hybrid-prototyping.aspx

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