DesignWare Technical Bulletin 

High-Quality, Silicon-Proven DesignWare IP Solutions for Advanced SoC Designs  

This quarterly newsletter provides you with the latest information on DesignWare® IP, including in-depth technical articles, white papers, videos, webinars, product announcements and more. As the industry's trusted IP provider, Synopsys is committed to providing you with the resources you need to help you lower integration risk and speed time-to-market.

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Featured Articles

ARC Insider: Top 5 Features to Consider When Choosing a Software Development Platform
Embedded software development is a significant part of the design effort for modern SoCs. This article explains what to look for in a software development system to get started quickly and accelerate code development.

  • Optimized Memory for Hardening CPU, GPU and DSP Cores - CPUs, GPUs, and DSPs used in mobile SoCs have different power, performance, and area requirements. Learn about memory design techniques that enable SoC designers to meet all of these seemingly conflicting goals.

  • Understanding the MIPI M-PHY - Standards bodies such as PCI-SIG and USB-IF are developing digital controllers that interoperate seamlessly with the M-PHY. Learn the basics of the MIPI M-PHY for success in using the emerging M-PCIe and SSIC protocols.

  • Developing High-Performance 28-nm Data Converters with the SAR-Based Architecture – See the performance results for 28-nm Successive-Approximation Register (SAR)-based architecture for high-speed, high-resolution DesignWare Analog-to-Digital Converters.

  • USB 3.1: What’s in a Name? – Learn the USB 3.1 terminology and nomenclature as defined in the new USB-IF specification, including the correct use of “Enhanced SuperSpeed,” “Gen 2,” and “10G,” to ensure accurate and efficient communication.

Tips & Tricks: Techniques for Improving QoR Using analyze_datapath_extraction
Efficient datapath extraction is essential in getting good QoR, particularly in designs with large datapath content. This article explains datapath analysis techniques that can be used to improve the QoR of designs.

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