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Understanding the MIPI M-PHY

By Sérgio Silva, Project Director, DesignWare MIPI M-PHY IP and Hezi Saar, Staff Product Marketing Manager, DesignWare MIPI PHY and Controller IP

Consumers today demand higher performance, feature-rich applications, and higher quality multimedia content in their mobile devices. To design these high-performance devices, designers need to contend with pin count and channel limitations (including the physical dimensions, cost, and package reliability) as well as bandwidth bottlenecks. At the same time, battery operated mobile devices strive for very low power consumption in active and idle periods with quick entry and exit times.

The high-speed MIPI® M-PHY is tailored for mobile systems and is becoming a popular physical layer solution. The M-PHY is designed to accommodate the intermittent nature of inter-chip communications and employs burst operation to toggle between data transmission and power saving states, effectively reducing power consumption.

As the M-PHY gains in popularity, standards bodies such as PCI-SIG and USB-IF are developing digital controllers that interoperate seamlessly with the M-PHY. Designers familiar with PCI-SIG’s PCI Express and USB-IF’s USB 3.0 need to understand the basics of the MIPI M-PHY for success using the emerging M-PCIe and SSIC protocols, as do any designers working on low-power consumer and mobile system-on-chips (SoCs).

MIPI M-PHY Basics
The MIPI M-PHY is a serial communication protocol for use in mobile systems where performance, power, and efficiency are key criteria. It is the foundation for several upper layer protocols which manage complex data transfer functions. Each of these protocols is optimized for its particular purpose, such as data storage, data transfer, display, camera, memory sharing, and radio interface. Scalability and modularity are also important features of the MIPI M-PHY, as these features allow designers to more easily adapt to evolving system and application requirements.

Architecture
The M-PHY’s basic unit is the lane, which can be a transmitter (M-TX) or receiver (M-RX). Each lane is treated as an independent unit and has its own configuration and data interface. A lane manager (associated with the protocol adapter) controls the line states (active/inactive) and, when several lanes are aggregated for higher throughput, manages clock compensation and lane alignment. A single link, constituted by an up- and downstream sub-link, handles chip-to-chip communication. Each sub-link can have one or more lanes aggregated to create an M-TX/M-RX pair. A clock multiplication unit (for example, phase-locked loop, or PLL) provides the necessary clocks to the lanes in the PHY.

As shown in Table 1, a MIPI M-PHY is divided into two distinct versions called “types”: Type-I and Type-II. M-PHY Type-I does not require a shared reference clock, which allows for media converters, such as range extenders or optical transceivers. M-PHY Type-II relies on a shared clock for simple PCB-level interconnect used in applications like radio front-end interfaces. Both Type-I and Type-II use the same kind of signaling in high-speed mode, but in low-speed mode, M-PHY Type-I uses a modulation scheme called Pulse Width Modulation (PWM) that embeds the data clock, while Type-II uses shared reference clock synchronous data transmission.

Understanding the MIPI M-PHY

Table 1: Features of MIPI M-PHY Type-I and Type-II

Transmission modes and speeds
M-PHYs support two main transmission modes/active states: low speed (LS), which supports 3 to 576 Mbps, and high speed (HS), which supports 1,248 to 5,824 Mbps per the M-PHY v3.0 specification. Each sub-link can support its own transmission mode. Highly asymmetric applications, like camera or display applications, can reduce the total link power consumption by fitting transmission modes to the traffic requirement on each sub-link.

High-speed transmission modes are called Gears: Gear1, Gear2, and Gear3. Each Gear is also divided into Rate A and Rate B, as shown in Table 2. A data rate deviation of ±2,000 ppm is permitted for each bit rate to allow for independent reference clock frequency shifts and power efficient integer frequency multiplier PLLs.

Systems supporting Gear3 must also support Gear2 and Gear1, which allows applications to change link speeds according to the requirements in runtime operation, thus further regulating the performance/power consumption ratio.

Understanding the MIPI M-PHY

Table 2: MIPI M-PHY high speed bit rates

Clocking flexibility
An M-PHY is able to operate in mesochronous or plesiochronous clock mode, as shown in Figure 1. In mesochronous operation, which is supported by both Type-I and Type-II M-PHYs, the M-TX and M-RX lanes share a reference clock and only phase recovery is necessary in high-speed operation. In plesiochronous operation, supported in M-PHY Type-I only, independent clock sources are used at each side. This implies frequency and phase recovery in high-speed operation.

Different clock references (e.g., different crystal oscillators) are also allowed between a Type-I M-TX and M-RX of the same lane. This reduces the required pin count for a communication link, eases PCB routing and system level layout of the constituting devices.

Understanding the MIPI M-PHY

Figure 1: Comparison of plesiochronous and mesochronous operation in MIPI M-PHY Type-1 and Type-II interfaces

Multiple power saving states
Whenever the PHY is not transmitting it falls back to the respective mode power saving state: Sleep when in a low-speed mode or Stall when in a high-speed mode (Figure 2). Quick exit and entry into these states is key to burst operation and is achieved within a range of a few symbol time units.

Per the MIPI M-PHY specification, Hibernate, the lowest power state, enables the M-PHY to reduce its activity to the lowest possible level but still retain its configuration and the ability to quickly wake up to resume data transmission in a few microseconds. The short entry and exit hibernate state latency is critical for saving power during idle states and fits the requirements of mobile applications.

The effective power consumption of the link is the weighted average of the power and time spent in each of the M-PHY states. The M-PHY’s average power consumption must take into account the power and time spent in all states during operation.

Understanding the MIPI M-PHY

Figure 2: Relative power consumption of MIPI M-PHY states

Burst operation
The MIPI M-PHY is optimized for burst communication — a.k.a. “hurry up and shut down.” In burst communication, data is quickly dispatched during the transmission mode and the M-PHY immediately returns to a power saving state afterwards. Burst communication is possible because of the M-PHY’s low burst transmission start and stop overhead; e.g., there is no need for the link to transmit idle data. An application can explore the periodic nature of transmission (I/O operations, display line, idle times, etc.) to fit the M-PHY’s power saving states to its own needs (Figure 3).

Understanding the MIPI M-PHY

Figure 3: Burst transmission and M-PHY states in a typical application

Synopsys and the MIPI Ecosystem
As an active contributor to the MIPI Alliance working groups, Synopsys plays a key role in supporting the mobile ecosystem by developing high-quality, interoperable DesignWare® MIPI IP solutions that enable designers to deploy new features into their next-generation mobile devices. Synopsys offers optimized MIPI and M-PHY-based interface IP such UniPro, UFS, SSIC, and M-PCIe. Utilizing a single-vendor solution allows designers to lower the risk and cost of integrating MIPI M-PHY-based interfaces into baseband and application processor integrated circuits (ICs), while speeding time-to-market of advanced semiconductor solutions for mobile devices.

For more information, download the white paper, Reducing Power Consumption in Mobile Applications with High-Speed Gear3 MIPI M-PHY IP.


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