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Issue 3, 2012
FinFET: The Promises and the Challenges
While the new multi-gate or tri-gate architectures, also known as FinFET technology, deliver superior levels of scalability, design engineers face significant challenges in creating designs that optimize the promise of this exciting new technology. Jamil Kawa, group director of the Solutions Group, Synopsys, and Andy Biddle, product marketing manager, Galaxy Implementation Platform, Synopsys, explain how Synopsys is working with foundry partners and design teams to help them accelerate innovation and get the best out of their investments in FinFETs.
Design metrics including performance, power, area, cost and time to market have not changed since the inception of the integrated circuit (IC) industry. In fact, Moore’s law is all about optimizing those parameters by driving to the smallest possible transistor size with each new technology generation. However, as process technologies continued to shrink towards 20-nanometers (nm), it became impossible to achieve a similar scaling of certain device parameters, particularly the power supply voltage, which is the dominant factor in determining dynamic power. Additionally, optimizing for one variable such as performance automatically translated to unwanted compromises in other areas like power.
Given the new emerging metric of performance per unit power (Koomey’s law), one major design optimization alternative designers have in FinFETs, as compared to planar technology, is much better performance at the same power budget, or equal performance at a much lower power budget.
From Moore’s Law, we can infer that FinFETs represent the most radical shift in semiconductor technology in over 40 years. When Gordon Moore came up with his “law” back in 1965, he had in mind a design of about 50 components. Today’s chips consist of billions of transistors and design teams strive for “better, sooner, cheaper” products with every new process node. However, as feature sizes have become finer, the perils of high leakage current due to short-channel effects and varying dopant levels have threatened to derail the industry’s progress to smaller geometries.
The FinFET transistor structure promises to rejuvenate the chip industry by rescuing it from the short-channel effects that limit device scalability faced by current planar transistor structures.
FinFET: A Technology Primer
FinFETs have their technology roots in the 1990s, when DARPA looked to fund research into possible successors to the planar transistor. A UC Berkeley team led by Dr. Chenming Hu proposed a new structure for the transistor that would reduce leakage current.
The Berkeley team suggested that a thin-body MOSFET structure would control short-channel effects and suppress leakage by keeping the gate capacitance in closer proximity to the whole of the channel. They proposed two possible structures (Figure 1).
Figure 1: Thin-body MOSFETs are the origin of today’s FinFET transistors
Rotating the DG structure, which has the potential to provide the lowest gate leakage current, enables easier manufacturing using standard lithography techniques as the gate electrodes become self-aligned and the layout is similar to that of a planar FET (Figure 2).
Modern FinFETs are 3D structures that rise above the planar substrate, giving them more volume than a planar gate for the same planar area. Given the excellent control of the conducting channel by the gate, which “wraps” around the channel, very little current is allowed to leak through the body when the device is in the off state. This allows the use of lower threshold voltages, which results in optimal switching speeds and power.
Figure 2: From planar DG FET to FinFET
Other research teams have shown that FinFETs are scalable as long as it is possible to scale the thickness of the channel. For example, KAIST has demonstrated a 3-nm FinFET in its lab.
The FinFET Promise
Leading foundries estimate the additional processing cost of 3D devices to be 2% to 5% higher than that of the corresponding Planar wafer fabrication. FinFETs are estimated to be up to 37% faster while using less than half the dynamic power or cut static leakage current by as much as 90%.
FinFETs also promise to alleviate problematic performance versus power tradeoffs. Designers can run the transistors faster and use the same amount of power, compared to the planar equivalent, or run them at the same performance using less power. This enables design teams to balance throughput, performance and power to match the needs of each application.
Design Challenges – Minimizing Impact
Increasingly, designers care less about packing more transistors on a die (Moore’s Law) and more about delivering the best performance per Watt for the application. Interestingly, Jonathan Koomey has shown that the energy efficiency of computers has doubled nearly every 18 months since the first computers were built in the 1950s. Koomey’s Law expands on Moore’s law, especially given that quoting channel lengths is becoming less relevant. Given the abundance of transistors per unit area in advanced nodes, designers would use multi-processors at lower voltage to get the same throughput of a fewer number of processors at a higher voltage, sacrificing some additional area for the sake of saving power at the same throughput level.
The foundries want to make the transition to FinFET processes as transparent and smooth as possible for the design community. In order to do that, the EDA and IP industries need to work behind the scenes to ensure that the tools understand and model the complexities involved. Design teams want to take advantage of the power, performance and area benefits that FinFETs offer while still getting to market quickly and painlessly through a familiar process of creating the RTL and taking it through a backend implementation process.
IP Design Challenges – Not Just Another Transistor
While developers can take a familiar design flow and work with FinFET technology in much the same way as their previous bulk CMOS designs, the quality of results they achieve will depend to a large extent on the quality of the IP they choose.
Developing optimized memory and standard cells (physical IP) for FinFET requires expertise and experience. An experienced design team will be able to exploit the features that FinFET structures offer in order to create the best physical IP and not leave any power savings or performance on the table.
In order to continue on the path of Moore’s Law – and Koomey’s Law – designers must be able to leverage the target technology for maximum benefit, and invariably, that means focusing on the details.
Synopsys has been working with industry and academic partners for several years to gain a detailed understanding of FinFET technology, and apply that knowledge to develop IP, tools and services for successful FinFET design.
As a leading tool and IP developer, Synopsys is uniquely qualified to provide specific FinFET tool methodologies and FinFET-based memory and standard cell IP to customers developing differentiated leading-edge products in a broad range of applications from mobile computing to enterprise.
As we move to FinFET, one of the challenges is the discrete size of the fin. Transistor width (W), which is one of the main variables for tweaking transistor sizes, is no longer a continuum. Discrete fin sizing brings a new variable in design, without any easy workarounds, that designers have never had to deal with before.
Furthermore, additional design levers usually utilized by the IP designer, such as varying the channel length or body biasing, are either much more restrictive or are of limited benefit due to the intrinsic characteristics of FinFET technology.
Another challenge has to do with the complexity of the model. The FinFET is a 3D structure that has a lot of subdivided resistance and capacitance compared with a planar structure. This 3D structure requires a more complex model and more data manipulation than planar transistors. The complexity of the model has implications for the whole backend flow including extraction, layout, DRC and LVS, for the engineers responsible for managing the design. Experience counts when it comes to optimizing FinFET designs efficiently in order to achieve the best quality of results.
When it comes to IP design, getting the best out of the new FinFET technology requires experience. Synopsys has spent several years understanding the characteristics of FinFET technology and applying those to create new standard cell architectures and memory compilers. Synopsys has successfully navigated through complex FinFET issues and has devised solutions for them. For example, there are specific challenges related to read-write access for memories. Synopsys has exploited the inherently low operating voltages of FinFETs to enable the design of memories with low retention voltages.
Another fundamental issue that determines a transistor’s performance is its stress profile – the mechanical stress that we deliberately introduce into the device to enhance its performance. Because of its vertical fin, the FinFET has a significantly different stress profile from a planar transistor. Synopsys has been collaborating with industry partners from an early stage to apply its Technology Computer-Aided Design (TCAD) tools to the task of accurately modeling FinFET stress profiles (for more information, see TCAD Tools).
Synopsys continues to work closely with the major foundries to accurately capture all of the intricacies of FinFET technology, and to create models that we can use within the entire design flow from concept to implementation, including SPICE modeling, extraction and physical IP design.
The FinFET Tool Story
- The foundry’s intent is to ensure the transition to FinFET is as transparent as possible, allowing users to seamlessly scale designs to increasingly smaller geometry processes. Maximum benefits with this technology will require implementation tools to minimize power consumption and maximize utilization and clock speed. FinFETs require some specific enhancements made in the following areas:
- TCAD Tools
- Mask Synthesis
- Transistor Models
- SPICE Simulation Tools
- RC Extraction Tools
- Physical Verification Tools
To harness the full potential of 3D FETs, wafer processing technologies are being developed to controllably dope the fin sidewalls and stress the fins to boost device performance. To support these efforts, TCAD tools are used by the foundries during development to guide and optimize the semiconductor fabrication process. An important example of the need for 3D TCAD simulation is in the process optimization of SRAM cells, where stress and doping proximity effects require that all transistors comprising the SRAM be simulated in a single structure. This is made possible by recent advances in 3D structure generation, mesh generation and parallel algorithms.
The small geometries targeted for FinFETs have introduced a concern with the impact of process variability on device and circuit performance. While these effects were negligible on higher geometry processes, they are now becoming first order effects. These variations caused by random dopant fluctuations, line edge roughness, layout induced stress, and other process variations ultimately manifest themselves as variations in device performance, in particular with threshold voltage shifts and local currents that impact timing and power. TCAD tools are used to simulate these effects and, ultimately, help build the device models used by EDA tools.
Synopsys has deployed Sentaurus TCAD (Figure 3) in FinFET research and development since 2005 at leading foundries, Integrated Device Manufacturers (IDMs) and research universities, and has made highly complex and sophisticated refinements to these tools as a result of this collaboration. These refinements include changes to our plasma-doping model, fin dimensional optimization to achieve device performance targets and modeling of the random process variations to improve device performance. Figure 3 shows an example of the 3D simulation performed by Sentaurus for p-channel FinFETs.
Figure 3: Stress fields in pFinFETs simulated with TCAD Sentaurus
Mask synthesis is a key component in advanced manufacturing, used to post- process the resultant layouts produced by EDA tools and help compensate for limitations and effects in the lithography process used in manufacturing. The advanced geometries targeted for FinFET are expected to require self-aligned double patterning (SADP) in deposition manufacturing steps to create the fins rather than defining the fins lithographically. As the fins are tall and thin, traditional lithography/OPC methods would result in line-edge roughness problems.
The Synopsys Proteus product provides a comprehensive and powerful environment for performing full-chip proximity correction, building models for correction and analyzing proximity effects on corrected and uncorrected IC layout patterns. These products are the mask synthesis tool of choice for IDMs and foundries building FinFET-based designs. Synopsys is closely engaged with the foundries on refining and deploying the Proteus SADP solution.
FinFETs introduce much higher complexities for resistance and parasitic capacitance. Additional information is needed in the model for source/drain resistance extensions, contact resistances fringing effects and the wider number of coupling capacitances introduced by the three dimensional structures. The new behaviors are captured in new standardized models used by spice simulators. The Berkeley Short-channel IGFET Model for Common Multi-Gate (BSIM-CMG) compact model is used by SPICE simulators to ensure accurate simulation of designs using these new devices.
SPICE Simulation Tools
The Synopsys SPICE and FastSPICE simulators have been used extensively by the leading FinFET foundries to validate correct and accurate functionality with the new BSIM-CMG models. These tools form the cornerstone for transistor level library and circuit design. The Synopsys HSPICE simulator has been selected as the gold standard for foundries introducing FinFETs. Synopsys has multiple simulators supporting the BSIM-CMG models, HSPICE® and FineSim™ SPICE for full SPICE accuracy and CustomSim™ and FineSim Pro for FastSPICE use.
Resistance/Capacitance (RC) Extraction Tools
The 3D nature of FinFETs and the multiple fins making up the transistors introduce a large number of new parasitic resistance and capacitances to be considered, modeled and extracted from the FinFET-based designs. Figure 4 shows some of the parasitics introduced by this technology.
Figure 4: FinFET Parasitics
The interconnect modeling of semiconductors has been standardized in the open source Interconnect Technology Format (ITF). This format has recently been extended to add the FinFET requirements.
Synopsys’ StarRC™ extraction tool has been enhanced to support the new ITF models and is extensively used in the extraction of FinFET-based designs. StarRC is certified by leading FinFET foundries and is the industry standard for signoff extraction.
Physical Verification Tools
Physical verification is another area affected by FinFET technology. The new runsets used by the physical verification tools are used to verify Logic versus Schematic (LVS) correctness, and Design Rule Checks (DRCs). FinFETs require LVS enhancements to support recognition of these new devices in the layout and enable parameter extraction and identification of proximity effects. Other LVS enhancements include new source-drain resistance calculations. A number of new design rules have been introduced including fin-to-fin spacing and fin widths.
Synopsys’ IC Validator physical verification product has been enhanced to support LVS and DRC for FinFETs. It is currently being used for the development of FinFET- based designs and IP.
Figure 5: Synopsys FinFET Technology
The Synopsys TCAD and complete Galaxy™ Implementation Platform of tools, including IC Compiler, Galaxy Custom Designer® and PrimeTime®, have already been used to tapeout 3D FET production designs and numerous test chips. Synopsys tools are ready for the next wave of FinFET technology adopters. Figure 5 shows the entire design flow from concept to implementation, including SPICE modeling, extraction and physical IP design.
Circuit designers can look forward to enjoying a relatively seamless transition and significant benefits from FinFET technology by leveraging Synopsys tools and IP. Synopsys is leading the industry in its efforts to create IP, tools, flows and expertise that will guide the design community towards the successful adoption of this radical shift in semiconductor technology.
Historically, design teams have transitioned their IP from older planar technologies to the latest process nodes by using their in-house design capabilities and IP re-use. FinFET technology has created new challenges for many of these design teams because their current tools and techniques may not enable them to design their IP optimally for FinFET processes, delaying time to market. FinFETs require a new generation of design experience, expertise and tools in order to get the most from the technology.
Synopsys has extensive experience and expertise with FinFETs and can help design teams to mitigate their risk in developing FinFET-based IP processes. As well as being an early developer of a vast portfolio of physical IP for FinFET, Synopsys is currently working alongside foundry partners and customer design teams to help them design highly differentiated products in order to win in highly competitive markets.
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About the Authors
Jamil Kawa joined Synopsys in 1998 and is currently a group director in the Solutions Group, working on advanced nodes technology development for memories and IP. He is also a member of the company’s Technology Roadmap Team and Patent Committee. Jamil has held a variety of positions at Synopsys and has worked on DFM/DFY, 3-T SRAM technology, corrugated substrate technology (for FinFET manufacturing), low power design, and structured ASICs research. Jamil served as chairman of the Custom Circuits committee of CICC for 2005-2007. He holds seven issued patents and six pending patents in the areas of circuits and design architecture and has authored/co-authored over 20 papers and articles. Jamil holds a Master’s degree in Electrical Engineering from the University of Michigan, Ann Arbor and an MBA from Santa Clara University.
Andy Biddle joined Synopsys in April 2012 through the Magma acquisition. He is currently a product marketing manager in the Implementation Group, responsible for marketing the Galaxy Implementation Platform for advanced technologies. Andy has over 30 years of experience in the semiconductor industry with the last five years working in EDA. He has held a number of senior positions including ASIC design, sales, business development, strategic marketing and product marketing. Andy holds a Bachelor of Science in Electrical and Electronic Engineering from London South Bank University.