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Office Location
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TaiwanSynopsys Taiwan Limited (Hsinchu)
4F-1, #28, Tai-Yuan Street,
Chupei City, Hsinchu Hsien 302, Taiwan
Tel: +886-3-552-5880
Fax: +886-3-552-5881
Email: tw_feedback@synopsys.com | Synopsys Taipei
Room 3108, 31F,
333 Keelung Road, Section 1
Taipei 110, Taiwan
Tel: +886-2-2345-3020
Fax: +886-2-2757-6009
Email: tw_feedback@synopsys.com |
Workshop Schedule 2013 | Date | Location | Workshop | Cost | | Dec 18-19 | Hsinchu | Hspice Essentials | NTD 10,000 | | Dec 20-21 | Hsinchu | Star-RC | NTD 10,000 | | Jan 10-11 | Hsinchu | VCS | NTD 10,000 | | Jan 10-11 | Taipei | IC Compiler 1 | NTD 10,000 | | Jan 15-16 | Taipei | HSIM | NTD 10,000 | | Jan 15-16 | Hsinchu | Formality | NTD 10,000 | | Jan 17-18 | Taipei | PrimeRail | NTD 10,000 | | Jan 17-18 | Hsinchu | FineSim | NTD 10,000 | | Jan 23-25 | Hsinchu | SystemVerilog Test Bench (SVTB) Language | NTD 15,000 | | Jan 29-31 | Hsinchu | Design Compiler 1 | NTD 15,000 | | Jan 31 | Taipei | Custom Environment (including Custom WaveView, CustomExplorer & CustomExplorer Ultra) | NTD 5,000 | | Feb 01 | Hsinchu | CustomSim (XA) | NTD 5,000 | | Feb 05-06 | Taipei | Hspice Essentials | NTD 10,000 | | Feb 20 | Hsinchu | SystemVerilog Assertion (SVA) Language | NTD 5,000 | | Feb 21-22 | Hsinchu | IC Compiler 1 | NTD 10,000 | | Mar 06-08 | Hsinchu | PrimeTime 1 | NTD 15,000 | | Mar 07-08 | Taipei | Star-RC | NTD 10,000 | | Mar 13-14 | Taipei | Hspice Advanced Topics | NTD 10,000 | | Mar 13-15 | Hsinchu | DFT Compiler 1 | NTD 15,000 | | Mar 15 | Taipei | NanoSim | NTD 5,000 | | Mar 21-22 | Hsinchu | SiliconSmart | NTD 10,000 | | Mar 22 | Taipei | IC Compiler 2 (CTS) | NTD 5,000 | | Mar 27-29 | Hsinchu | SystemVerilog Verification Using UVM Methodology (SVTB-UVM) | NTD 15,000 | | Apr 09-10 | Hsinchu | IC Compiler 1 | NTD 10,000 | | Apr 10-12 | Taipei | Design Compiler 1 | NTD 15,000 | | Apr 11-12 | Hsinchu | PrimeRail | NTD 10,000 | | Apr 16-17 | Taipei | VCS | NTD 10,000 | | Apr 17 | Hsinchu | IC Compiler 2 (HDP) | NTD 5,000 | | Apr 18-19 | Hsinchu | TetraMAX 1 | NTD 10,000 | | Apr 24-26 | Taipei | SystemVerilog Test Bench (SVTB) Language | NTD 15,000 | | Apr 25-26 | Hsinchu | Hspice Essentials | NTD 10,000 | | May 08-09 | Hsinchu | SystemVerilog Verification Using VMM Methodology (SVTB–VMM) | NTD 10,000 | | May 10 | Hsinchu | Custom Environment (including Custom WaveView, CustomExplorer & CustomExplorer Ultra) | NTD 5,000 | | May 14-15 | Taipei | FineSim | NTD 10,000 | | May 16-17 | Hsinchu | Low Power Flow : HLD (Front End) | NTD 10,000 | | May 21-22 | Taipei | IC Compiler 1 | NTD 10,000 | | May 23-24 | Hsinchu | Star-RC | NTD 10,000 | | May 24 | Taipei | SystemVerilog Assertion (SVA) Language | NTD 5,000 | | May 30-31 | Taipei | Formality | NTD 10,000 | | Jun 05-06 | Hsinchu | Hspice Advanced Topics | NTD 10,000 | | Jun 06 | Taipei | CustomSim (XA) | NTD 5,000 | | Jun 19-21 | Hsinchu | Design Compiler 1 | NTD 15,000 | | Jun 27-18 | Hsinchu | IC Compiler 1 | NTD 10,000 | | Jul 03-05 | Hsinchu | PrimeTime 1 | NTD 15,000 | | Jul 09-10 | Hsinchu | Hspice Essentials | NTD 10,000 | | Jul 11-12 | Hsinchu | VCS | NTD 10,000 | | Jul 11-12 | Taipei | SiliconSmart | NTD 10,000 | | Jul 17-19 | Hsinchu | SystemVerilog Test Bench (SVTB) Language | NTD 15,000 | | Jul 24-26 | Taipei | SystemVerilog Verification Using VMM Methodology (SVTB–VMM) | NTD 15,000 | | Jul 25-26 | Hsinchu | HSIM | NTD 10,000 | | Aug 01-02 | Taipei | Star-RC | NTD 10,000 | | Aug 07 | Hsinchu | NanoSim | NTD 5,000 | | Aug 08-09 | Hsinchu | PrimeRail | NTD 10,000 | | Aug 15-16 | Taipei | IC Compiler 1 | NTD 10,000 | | Aug 15-16 | Hsinchu | NanoTime | NTD 10,000 | | Aug 21 | Hsinchu | SystemVerilog Assertion (SVA) Language | NTD 15,000 | | Aug 22-23 | Hsinchu | SystemVerilog Verification Using VMM Methodology (SVTB–VMM) | NTD 15,000 | | Aug 28-30 | Hsinchu | DFT Compiler 1 | NTD 15,000 | | Sep 03 | Hsinchu | CustomSim (XA) | NTD 5,000 | | Sep 04-06 | Hsinchu | Design Compiler 1 | NTD 15000 | | Sep 10 | Hsinchu | Custom Environment (including Custom WaveView, CustomExplorer & CustomExplorer Ultra) | NTD 5,000 | | Sep 11-12 | Hsinchu | Formality | NTD 10,000 | | Sep 13 | Hsinchu | NanoTime Ultra | NTD 5,000 | | Sep 25 | Hsinchu | IC Compiler 2 (CTS) | NTD 5,000 | | Sep 26-27 | Hsinchu | FineSim | NTD 10,000 | | Oct 01-02 | Hsinchu | Hspice Essentials | NTD 10,000 | | Oct 03-04 | Hsinchu | IC Compiler 1 | NTD 10,000 | | Oct 15-16 | Hsinchu | TetraMAX 1 | NTD 10,000 | | Oct 17-18 | Hsinchu | Star-RC | NTD 10,000 | | Oct 22-23 | Hsinchu | Hspice Advanced Topics | NTD 10,000 | | Oct 23 | Taipei | IC Compiler 2 (HDP) | NTD 5,000 | | Oct 24-25 | Hsinchu | SiliconSmart | NTD 10,000 | | Oct 29-31 | Hsinchu | SystemVerilog Verification Using UVM Methodology (SVTB–UVM) | NTD 15,000 | | Oct 29-31 | Taipei | PrimeTime 1 | NTD 15,000 |
| Workshop | Cost | Date and Location | | Open Vera Language and VERA | NTD 15,000 | By Request | | Magellan | NTD 10,000 | By Request | | Leda | NTD 5000 | By Request | | PrimeTime SI | NTD 5000 | By Request | | Power Compiler | NTD 10,000 | By Request | | Low Power Flow: Physical Implementation (Back End) | NTD 10,000 | By Request | | Astro 1 | NTD 15,000 | By Request | | Hercules | NTD 10,000 | By Request | | Custom Designer (including Custom Designer SE (Schematic Editor ), Custom Designer LE (Layout Editor)) | NTD 15,000 | By Request |
** Synopsys reserves the right to cancel or re-schedule the workshops ** Daily Class Time: 9:00am - 5:00pm Download Training Schedule (PDF) Registration Registration Form(PDF) Please fax registration forms to the following number. Fax: (03)5525883 Tel: (03)5525880 ext. 81878 Ms. Chen
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