Taiwan 

Office Location 
Taiwan

Synopsys Taiwan Co., Ltd. (Hsinchu)
No.25, Industry East Road IV,
Science-Based Industrial Park,
Hsinchu 300, Taiwan
Tel: +886-3-579-4567
Fax: +886-3-579-9000
Email: tw_feedback@synopsys.com

Synopsys Taipei
Room 3108, 31F,
333 Keelung Road, Section 1
Taipei 110, Taiwan
Tel: +886-2-2345-3020
Fax: +886-2-2757-6009
Email: tw_feedback@synopsys.com


To register for a course and view full course descriptions, visit the new Taiwan Training page

Workshop Schedule 2016

DateLocationWorkshopCost
Nov 24-25HsinchuStar-RCNTD 10,000
Dec 07-09HsinchuSystemVerilog TestbenchNTD 15,000
Dec 15-16HsinchuHspice EssentialsNTD 10,000

Workshop Schedule 2017

DateLocationWorkshopCost
Jan 10-11TaipeiCustomSim-XA Essentials and Mixed Signal Verification (XA-VCS)NTD10,000
Jan 11-13HsinchuDesign CompilerNTD15,000
Jan 12-13TaipeiPrimeRailNTD10,000
Jan 17-18HsinchuSiliconSmart 101NTD10,000
Jan 18-20TaipeiIC Compiler Block-Level ImplementationNTD15,000
Jan 19-20HsinchuFormality (Functional Equivalence Checking)NTD10,000
Feb 08-10HsinchuUVM 1.2NTD15,000
Feb 09-10TaipeiStar-RCNTD10,000
Feb 15-17HsinchuIC Compiler II: Block-level ImplementationNTD15,000
Feb 22-24HsinchuPrimeTimeNTD15,000
Mar 10HsinchuFineSim EssentialsNTD5,000
Mar 15-17HsinchuDFT CompilerNTD15,000
Mar 22HsinchuSystemVerilog AssertionsNTD5,000
Mar 23-24HsinchuIC Compiler II: SoC Design PlanningNTD10,000
Apr 11-12HsinchuStar-RCNTD10,000
Apr 12-14TaipeiSystemVerilog TestbenchNTD15,000
Apr 13-14HsinchuPrimeRailNTD10,000
Apr 19-21HsinchuTetraMAXNTD15,000
Apr 26-28HsinchuIC Compiler II: Block-level ImplementationNTD15,000
May 10-12TaipeiDesign CompilerNTD15,000
May 16HsinchuPower-Aware Verification with VCS-NLP and UPFNTD5,000
May 17HsinchuDesign Compiler 2 : Low PowerNTD5,000
May 18-19TaipeiFormality (Functional Equivalence Checking)NTD10,000
May 23-25HsinchuIC Compiler Block-Level ImplementationNTD15,000
May 24-25TaipeiHspice EssentialsNTD10,000
Jun 07-09TaipeiUVM 1.2NTD15,000
Jun 14-15TaipeiStar-RCNTD10,000
Jun 15-16HsinchuCustomSim-XA Essentials and Mixed Signal Verification (XA-VCS)NTD10,000
Jun 21-23HsinchuPrimeTimeNTD15,000
Jun 28-30HsinchuIC Compiler II: Block-level ImplementationNTD15,000
Jul 20-21TaipeiSiliconSmart 101NTD10,000
July 26-28HsinchuSystemVerilog TestbenchNTD15,000
Aug 09-11TaipeiIC Compiler Block-Level ImplementationNTD15,000
Aug 16-18HsinchuDFT CompilerNTD15,000
Aug 22-23HsinchuStar-RCNTD10,000
Aug 24-25HsinchuPrimeRailNTD10,000
Sep 06-08HsinchuTetraMAXNTD15,000
Sep 13-15HsinchuDesign CompilerNTD15,000
Sep 15TaipeiFineSim EssentialsNTD5,000
Sep 20-22HsinchuUVM 1.2NTD15,000
Sep 26-27HsinchuFormality (Functional Equivalence Checking)NTD10,000
Oct 18-20TaipeiPrimeTimeNTD15,000
Oct 18-20HsinchuIC Compiler Block-Level ImplementationNTD15,000
Oct 26-27HsinchuHspice EssentialsNTD10,000

** Synopsys reserves the right to cancel or re-schedule the workshops **

Daily Class Time: 9:30am - 5:00pm
Download Training Schedule (PDF)