DesignWare DDR IP Solutions 

DesignWare DDR IP Solutions

Overview 

The DesignWare® DDR Memory Interface IP is a family of complete system-level IP solutions for system-on-chips (SoCs) requiring an interface to one or more of the broad range of high-performance DDR4, DDR3, DDR2, LPDDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs or memory modules (DIMMs). Optimized for high data bandwidth, low power and enhanced signaling features, the complete DesignWare DDR Memory Interface IP solution includes a choice of scalable digital controllers, an integrated hard macro PHY delivering silicon-proven memory system performance of up to 3200 Mbps per bit, and verification IP.

There are seven Synopsys DesignWare DDR PHY IP cores to choose from, as detailed in PHY Details tab, below.

All of the DFI-compatible DDR PHYs are supported by Synopsys' unique DesignWare DDR PHY Compiler.

Synopsys' DesignWare Enhanced Universal DDR Memory and Protocol Controller IP features a DFI-compliant interface, low latency and low gate count while offering high bandwidth. Optional market-specific features like AMBA AXI/AXI4 Quality of Service (QoS) and Reliability, Availability and Serviceability (RAS) features allow you to match the area and capabilities of the controllers to your needs. Check out DesignWare DDR Explorer for efficient DDR memory subsystem optimization.

Synopsys is the #1 DDR IP provider for a reason: see why Synopsys is the Trusted DDR IP Partner.

DDR Complete Solution Datasheet

 
  • DDR4
  • Complete DDR4 IP solutions for up to 3200 Mbps 

Enhanced DDR Controllers
DDR memory and protocol controller IP supporting JEDEC standard DDR4, DDR3, DDR2, LPDDR4, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs. They support ARM® AMBA® (AXI4, AXI3) busses as well as a native bus and include QoS and RAS enhancements. Use DDR Explorer for configuration optimization.  
PDF DOWNLOAD DATASHEET (PDF)


DDR4/3 PHYs
High-performance PHY with embedded calibration processor supporting DDR4 up to 3200 Mbps and DDR3/DDR3L up to 2133 Mbps.
PDF DOWNLOAD DATASHEET (PDF)


DDR4 multiPHY
Supports DDR4 up to 2667 Mbps, DDR3/3L/3U up to 2133 Mbps and LPDDR3/2 up to 2133 Mbps
PDF DOWNLOAD DATASHEET (PDF)


IP Prototyping Kits
Accelerate IP prototyping, software development and integration


IP Virtualizer Development Kits
Bring-up, debug, and test software with ARM-based SDKs using a virtual prototype


Interface IP Subsystems
Reduce the overall effort and cost of assembling and integrating IP into an SoC


Verification IP
Verify DDR interfaces

  • LPDDR4
  • Complete LPDDR4 IP solutions for low power, 2133 Mbps applications 

Enhanced DDR Controllers
DDR memory and protocol controller IP supporting JEDEC standard DDR4, DDR3, DDR2, LPDDR4, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs. They support ARM® AMBA® (AXI4, AXI3) busses as well as a native bus and include QoS and RAS enhancements. Use DDR Explorer for configuration optimization.  
PDF DOWNLOAD DATASHEET (PDF)


LPDDR4 multiPHY
Supports LPDDR4 and DDR4 up to 3200 Mbps, LPDDDR3 and DDR3/3L/3U up to 2133 Mbps
PDF DOWNLOAD DATASHEET (PDF)


IP Prototyping Kits
Accelerate IP prototyping, software development and integration


IP Virtualizer Development Kits
Bring-up, debug, and test software with ARM-based SDKs using a virtual prototype


Interface IP Subsystems
Reduce the overall effort and cost of assembling and integrating IP into an SoC


Verification IP
Verify DDR interfaces

  • DDR3/3L/3U
  • Complete DDR3 IP solutions: Controllers, PHYs, VIP, Dev. Kits & more 

Enhanced DDR Controllers
DDR memory and protocol controller IP supporting JEDEC standard DDR4, DDR3, DDR2, LPDDR4, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs. They support ARM® AMBA® (AXI4, AXI3) busses as well as a native bus and include QoS and RAS enhancements. Use DDR Explorer for configuration optimization.  
PDF DOWNLOAD DATASHEET (PDF)


Basic DDR Controllers
DDR memory and protocol controller provides simple support for the JEDEC standard DDR3, DDR2, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs.
PDF DOWNLOAD DATASHEET (PDF)


DDR4/3 PHYs
High-performance PHY with embedded calibration processor supporting DDR4 up to 3200 Mbps and DDR3/DDR3L up to 2133 Mbps.
PDF DOWNLOAD DATASHEET (PDF)


DDR4 multiPHY
Supports DDR4 up to 2667 Mbps, DDR3/3L/3U up to 2133 Mbps and LPDDR3/2 up to 2133 Mbps
PDF DOWNLOAD DATASHEET (PDF)


DDR3/2 SDRAM PHYs
Supports DDR3/3L and DDR2 up to 2133 Mbps
PDF DOWNLOAD DATASHEET (PDF)


Gen 2 DDR multiPHY
Supports LPDDR3/2 and DDR3/3L/3U up to 2133 Mbps
PDF DOWNLOAD DATASHEET (PDF)


DDR multiPHY
Supports LPDDR2, LPDDR, DDR3/3L/3U, and DDR2 up to 1066 Mbps
PDF DOWNLOAD DATASHEET (PDF)


DDR2/3-Lite/mDDR SDRAM PHY
Area and feature-optimized IP solution operating at up to 1066 Mbps using Mobile DDR, DDR2 or DDR3 SDRAMs
PDF DOWNLOAD DATASHEET (PDF)


IP Prototyping Kits
Accelerate IP prototyping, software development and integration


IP Virtualizer Development Kits
Bring-up, debug, and test software with ARM-based SDKs using a virtual prototype


Interface IP Subsystems
Reduce the overall effort and cost of assembling and integrating IP into an SoC


Verification IP
Verify DDR interfaces

  • LPDDR3
  • Complete LPDDR3 IP solutions: Controllers, PHYs, VIP, Dev. Kits & more 

Enhanced DDR Controllers
DDR memory and protocol controller IP supporting JEDEC standard DDR4, DDR3, DDR2, LPDDR4, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs. They support ARM® AMBA® (AXI4, AXI3) busses as well as a native bus and include QoS and RAS enhancements. Use DDR Explorer for configuration optimization.
PDF DOWNLOAD DATASHEET (PDF)


Basic DDR Controllers
DDR memory and protocol controller provides simple support for the JEDEC standard DDR3, DDR2, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs.
PDF DOWNLOAD DATASHEET (PDF)


LPDDR4 multiPHY
Supports LPDDR4 and DDR4 up to 3200 Mbps, LPDDDR3 and DDR3/3L/3U up to 2133 Mbps
PDF DOWNLOAD DATASHEET (PDF)


DDR4 multiPHY
Supports DDR4 up to 2667 Mbps, DDR3/3L/3U up to 2133 Mbps and LPDDR3/2 up to 2133 Mbps
PDF DOWNLOAD DATASHEET (PDF)


Gen 2 DDR multiPHY
Supports LPDDR3/2 and DDR3/3L/3U up to 2133 Mbps
PDF DOWNLOAD DATASHEET (PDF)


IP Virtualizer Development Kits
Bring-up, debug, and test software with ARM-based SDKs using a virtual prototype


Interface IP Subsystems
Reduce the overall effort and cost of assembling and integrating IP into an SoC


Verification IP
Verify DDR interfaces

  • DDR2
  • Complete DDR2 IP solutions: Controllers, PHYs, VIP, Dev. Kits & more 

Enhanced DDR Controllers
DDR memory and protocol controller IP supporting JEDEC standard DDR4, DDR3, DDR2, LPDDR4, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs. They support ARM® AMBA® (AXI4, AXI3) busses as well as a native bus and include QoS and RAS enhancements. Use DDR Explorer for configuration optimization.
PDF DOWNLOAD DATASHEET (PDF)


Basic DDR Controllers
DDR memory and protocol controller provides simple support for the JEDEC standard DDR3, DDR2, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs.
PDF DOWNLOAD DATASHEET (PDF)


DDR multiPHY
Supports LPDDR2, LPDDR, DDR3/3L/3U, and DDR2 up to 1066 Mbps
PDF DOWNLOAD DATASHEET (PDF)


DDR3/2 SDRAM PHY
Supports DDR3/3L and DDR2 up to 2133 Mbps
PDF DOWNLOAD DATASHEET (PDF)


DDR2/3-Lite/mDDR SDRAM PHY
Area and feature-optimized IP solution operating at up to 1066 Mbps using Mobile DDR, DDR2 or DDR3 SDRAMs
PDF DOWNLOAD DATASHEET (PDF)


IP Virtualizer Development Kits
Bring-up, debug, and test software with ARM-based SDKs using a virtual prototype


Interface IP Subsystems
Reduce the overall effort and cost of assembling and integrating IP into an SoC


Verification IP
Verify DDR interfaces

  • LPDDR2
  • Complete LPDDR2 IP solutions: Controllers, PHYs, VIP, Dev. Kits & more 

Enhanced DDR Controllers
DDR memory and protocol controller IP supporting JEDEC standard DDR4, DDR3, DDR2, LPDDR4, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs. They support ARM® AMBA® (AXI4, AXI3) busses as well as a native bus and include QoS and RAS enhancements. Use DDR Explorer for configuration optimization.
PDF DOWNLOAD DATASHEET (PDF)


Basic DDR Controllers
DDR memory and protocol controller provides simple support for the JEDEC standard DDR3, DDR2, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs.
PDF DOWNLOAD DATASHEET (PDF)


DDR4 multiPHY
Supports DDR4 up to 2667 Mbps, DDR3/3L/3U up to 2133 Mbps and LPDDR3/2 up to 2133 Mbps
PDF DOWNLOAD DATASHEET (PDF)


Gen 2 DDR multiPHY
Supports LPDDR3/2 and DDR3/3L/3U up to 2133 Mbps
PDF DOWNLOAD DATASHEET (PDF)


DDR multiPHY
Supports LPDDR2, LPDDR, DDR3/3L/3U, and DDR2 up to 1066 Mbps
PDF DOWNLOAD DATASHEET (PDF)


IP Virtualizer Development Kits
Bring-up, debug, and test software with ARM-based SDKs using a virtual prototype


Interface IP Subsystems
Reduce the overall effort and cost of assembling and integrating IP into an SoC


Verification IP
Verify DDR interfaces

  • LPDDR/mDDR
  • Complete LPDDR IP solutions: Controllers, PHYs, VIP, Dev. Kits & more 

Enhanced DDR Controllers
DDR memory and protocol controller IP supporting JEDEC standard DDR4, DDR3, DDR2, LPDDR4, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs. They support ARM® AMBA® (AXI4, AXI3) busses as well as a native bus and include QoS and RAS enhancements. Use DDR Explorer for configuration optimization.
PDF DOWNLOAD DATASHEET (PDF)


Basic DDR Controllers
DDR memory and protocol controller provides simple support for the JEDEC standard DDR3, DDR2, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs.
PDF DOWNLOAD DATASHEET (PDF)


DDR multiPHY
Supports LPDDR2, LPDDR, DDR3/3L/3U, and DDR2 up to 1066 Mbps
PDF DOWNLOAD DATASHEET (PDF)


DDR2/3-Lite/mDDR SDRAM PHY
Area and feature-optimized IP solution operating at up to 1066 Mbps using Mobile DDR, DDR2 or DDR3 SDRAMs
PDF DOWNLOAD DATASHEET (PDF)


IP Virtualizer Development Kits
Bring-up, debug, and test software with ARM-based SDKs using a virtual prototype


Interface IP Subsystems
Reduce the overall effort and cost of assembling and integrating IP into an SoC


Verification IP
Verify DDR interfaces

DesignWare DDR PHY SDRAMs Supported /
Maximum Data Rate
Interface to Memory
Controller
Typical Application
DDR4/3 PHY DDR4 / 3200 Mbps
DDR3 / 2133 Mbps
DFI 4.0 Design in 28-nm and below that requires high-performance DDR4/3 support up to 3200 Mbps
DDR4 multiPHY DDR4 / 2667 Mbps
DDR3 / 2133 Mbps
LPDDR2 / 1066 Mbps
LPDDR3 / 2133 Mbps
DFI 3.1 Design in 28-nm and below that requires high-performance DDR4/3 support up to 2667 Mbps and/or high performance mobile SDRAM support (LPDDR3/2) up to 2133 Mbps.
LPDDR4 multiPHY LPDDR4 / 3200 Mbps
LPDDR3 / 2133 Mbps
DDR4 / 3200 Mbps
DDR3 / 2133 Mbps
DFI 4.0 Design in 28-nm and below, including 14/16-nm FinFET, that requires high-performance mobile SDRAM support (LPDDR4/3) up to 3200 Mbps and/or high performance DDR4/3 support up to 3200 Mbps for small memory subsystems.
Gen 2 DDR multiPHY DDR3 / 2133 Mbps
LPDDR2 / 1066 Mbps
LPDDR3 / 2133 Mbps
DFI 3.1 Design in 28-nm and below that requires high-performance mobile SDRAM support (LPDDR3/2) up to 2133 Mbps and/or high performance DDR3 support up to 2133 Mbps.
DDR multiPHY DDR3 / 1066 Mbps
DDR2 / 1066 Mbps
LPDDR / 400 Mbps
LPDDR2 / 1066 Mbps
DFI 2.1 Design in 65 - 28-nm that requires DDR3 and/or DDR2 support up to 1066 Mbps along with LPDDR/LPDDR2 support.
DDR3/2 SDRAM PHY DDR3 / 2133 Mbps
DDR2 / 1066 Mbps
DFI 2.1 Design in 65 - 28-nm that requires high performance DDR3 up to 2133 Mbps.
DDR2/3-Lite/mDDR DDR3 / 1066 Mbps
DDR2 / 1066 Mbps
LPDDR / 400 Mbps
DFI 2.1 Design in 65 - 40-nm that requires DDR3 and/or DDR2 support up to 1066 Mbps along with LPDDR support.


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