The DesignWare® DDR Memory Interface IP is a family of complete system-level IP solutions for system-on-chips (SoCs) requiring an interface to one or more of the broad range of high-performance DDR4, DDR3, DDR2, LPDDR, LPDDR2 and LPDDR3 SDRAMs or memory modules (DIMMs). Optimized for high data bandwidth, low power and enhanced signaling features, the complete DesignWare DDR Memory Interface IP solution includes a choice of scalable digital controllers, an integrated hard macro PHY delivering memory system performance of up to 2667 Mbps per bit and verification IP.
There are five Synopsys DesignWare DDR PHY IP cores to choose from, as detailed in PHY Details tab, below.
All of the DFI-compatible DDR PHYs are supported by Synopsys' unique DesignWare DDR PHY Compiler.
There are two types of DDR digital controller IP cores to choose from: Synopsys' DesignWare Universal DDR Memory Controller (including the Enhanced version) and Protocol Controller IP cores feature a DFI 2.1 or 3.1 compliant interface (DFI3.1 is backwards compatible with DFI 2.1), low latency and low gate count while offering flexibility of clock frequency ratios between PHY and controller to allow easier timing closure in slower processes and lower latency in faster technologies.