DesignWare Standard DDR Controllers 

Overview 

The DesignWare Standard DDR controller family consists of two high performance families of controller components, the DDR Protocol Controllers (PCTLs) and the DDR Memory Controllers (MCTLs).

The family of PCTLs deliver efficient bandwidth with minimum latency and provides the designers with transparent access and complete control of the memory subsystem. The PCTL serves the memory control needs of applications with simple transactions that do not require an internal scheduler, and can also be deployed with custom-designed memory management units. The PCTL SoC application bus interface supports a lowest-latency "native application interface" (NIF). The DDR2/3-Lite PCTL is compatible with both the DesignWare DDR2/3-Lite PHY IP. The DDR3/2 PCTL is compatible with DesignWare DDR3/2 PHY IP.

The family of MCTLs offer an advanced multi-port memory controller which accepts memory access requests from up to 32 application-side host ports and applies re-ordering rules and port prioritization to optimize the command execution and improve data bus utilization. Application-side interfaces can be connected to the MCTL either through the standard AMBA AXI/AHB bus interfaces or via Synopsys custom-defined HMI or PMI interfaces. The DDR2/3-Lite MCTL is compatible with the DesignWare DDR2/3-Lite PHY IP. The DDR3/2 MCTL is compatible with DesignWare DDR3/2 PHY IP.

All products in the DesignWare Standard DDR controller family include software configuration registers, which are accessed through a separate register interface.

  • Products
 

 
Low latency, area efficient digital interface between a single on-chip interface and a DDR2/DDR, DDR2/3-Lite or DDR2/3-Lite/mDDR PHY. Enables custom scheduler, arbitration and application ports
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Low latency, area efficient digital interface between a single on-chip interface and a DDR3/2 PHY. Enables custom scheduler, arbitration and application ports
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Efficient digital interface between up to 32 on-chip application buses and a DDR2/DDR PHY. Provides QoS, arbitration and optimized memory transactions
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Efficient digital interface between up to 32 on-chip application buses and a DDR2/3-Lite/mDDR or DDR2/3-Lite or DDR2/DDR PHY. Provides QoS, arbitration and optimized memory transactions
PDF DOWNLOAD DATASHEET


 
Efficient digital interface between up to 32 on-chip application buses and a DDR3/2 PHY. Provides QoS, arbitration and optimized memory transactions