DesignWare MIPI IP Solutions 

Overview 

DesignWare® MIPI® IP solutions enable the interface between system-on-chips (SoCs), application processors, baseband processors, and peripheral devices. Synopsys’ MIPI IP solutions include a broad portfolio of digital controllers and silicon-proven PHY IP to support the D-PHY, M-PHY®, DigRF v4 and 3G, Camera Serial Interface (CSI-2), Display Serial Interface (DSI), UniPro®, and UFS specifications.

As an active contributor to the MIPI Alliance working groups, Synopsys continues to play a key role in supporting the mobile ecosystem by developing high-quality, interoperable MIPI IP solutions that enable designers to deploy new features into their next-generation mobile devices. Utilizing a single-vendor solution allows designers to lower the risk and cost of integrating MIPI interfaces into baseband and application processor integrated circuits (ICs), while speeding time-to-market of advanced semiconductor solutions for mobile devices.

Download Datasheet


Understanding MIPI
  • Products
 
  • M-PHY
  • MIPI M-PHY supporting seven protocolsmore

 
Scalable, low-power, low-latency and compact solution supporting LLI, SSIC, M-PCIe, DigRFv4, UniPro, UFS, and CSI-3 protocols
PDF DOWNLOAD DATASHEET

  • UniPro
  • Highly configurable, synthesizable controller for host and device ICsmore

 
Compliant with MIPI UniPro v 1.41 and supports all host and device configurations for JEDEC UFS, and MIPI DSI-2
PDF DOWNLOAD DATASHEET

  • UFS Host
  • Host controller for JEDEC UFS standard interfacemore

 
Mobile storage serial interface compliant with the JEDEC UFS Architecture Specification (UFS) and the JEDEC UFSHCI
PDF DOWNLOAD DATASHEET

  • DigRF v4
  • Master controller for MIPI DigRF v4 standard interfacemore

 
Area, power and pin count efficient interface for advanced LTE and Mobile WiMax Baseband processors
PDF DOWNLOAD DATASHEET

  • DigRF 3G
  • Controllers and PHYs for MIPI DigRF 3G standard interfacemore

 
Area, power and pin count efficient digital interface for Baseband and RFIC targeting dual-mode 2.5G / 3G mobile phone systems


  • D-PHY
  • Physical layer for MIPI CSI-2, DSI and UniPro standard interfacesmore

 
High-performance, low power MIPI D-PHY. Up to 4 lanes serial interface available in advanced technology nodes
PDF DOWNLOAD DATASHEET

  • CSI-2
  • Synthesizable controller for MIPI CSI-2 host applicationmore

 
Compliant to MIPI CSI-2 specification rev 1.0. Supports 1 to 4 Rx data lanes with D-PHY PPI interface and 32bit pixel output format
PDF DOWNLOAD DATASHEET

  • DSI
  • Synthesizable controller for MIPI DSI host applicationmore

 
Compliant to the DSI specification rev 1.01. Up to 4 data lanes with D-PHY PPI interface and support DPI-2, DBI-2 and DCS specifications.
PDF DOWNLOAD DATASHEET

  • Verification IP
  • Verifies MIPI CSI-2, DigRFv4, DSI and M-PHY interfaces 

CSI-2 Verification IP
CSI-2 VIP can act as a transmitter or receiver and supports high speed and ultra low power. It is based on Synopsys’ SystemVerilog UVM architecture and supports all popular simulators.


DigRFv4 Verification IP
DigRFv4 VIP acts as a transmitter or receiver, includes support for M-PHY and RMMI interfaces. Based on Synopsys’ SystemVerilog UVM architecture and supports all popular simulators.


DSI Verification IP
DSI VIP acts as a transmitter or receiver and supports for high speed and ultra low power. Based on Synopsys’ SystemVerilog UVM architecture and supports all popular simulators.


M-PHY Verification IP
M-PHY VIP supports M-PHY version 2.0 and supports the serial and RMMI interfaces. It is based on Synopsys’ SystemVerilog UVM architecture and supports all popular simulators.



NewsArticlesBlogsWhite PapersWebinarsVideosNewslettersCustomer Successes