DesignWare IP Solutions for PCI Express 

Overview 

Synopsys’ complete, silicon-proven DesignWare® IP for PCI Express® solution includes a suite of digital core IP, PHY IP and verification IP (VIP), all of which are compliant to the PCI Express 3.0, 2.1 and 1.1 (Gen3/Gen2/Gen1) and PIPE specifications. In addition, Synopsys supports the M-PCIe ECN with silicon-proven M-PHY and M-PCIe Controller IP. As the leading supplier of PCI Express IP, Synopsys’ DesignWare PCI Express IP solution has gone through extensive third-party interoperability testing with products shipping in volume production. The strict quality measures combined with an expert technical support team enables designers to accelerate time-to-market and reduce integration risk for next-generation desktop, mobile, consumer and communication system-on-chips (SoCs).

More than 1,000 customers use DesignWare IP for PCI Express in their SoCs. See why Synopsys is the Trusted PCIe IP Partner.

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  • Endpoint
  • Configurable PCIe 3.0, 2.1 and 1.1 IP for Endpoint applicationsmore

 
Implements the port logic required for a PCIe Endpoint and it is compliant with the PCI Express 3.0, 2.1 and 1.1 and PCI-SIG SR-IOV specifications.
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  • Root Port
  • Configurable PCIe 3.0, 2.1 and 1.1 IP for Root Port applicationsmore

 
Implements the port logic required for a PCIe Root Complex and it is compliant with the PCI Express 3.0, 2.1 and 1.1 specifications
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  • Dual Mode
  • Configurable PCIe 3.0, 2.1 and 1.1 IP for RC or EP applicationsmore

 
Implements the port logic required for both a PCIe Root Complex and Endpoint and it is compliant with the PCIe 3.0, 2.1 and 1.1 and PCI-SIG SR-IOV specifications.
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Implements the upstream or downstream port logic required for a PCIe Switch or Bridge and it is compliant with the PCI Express 3.0, 2.1 and 1.1 specifications.
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  • M-PCIe
  • Configurable IP for PCIe 3.0, 2.1, 1.1, M-PCIe ECN and RMMI specmore

 
Scalable controller IP that implements the port logic required to build a Root Port, Endpoint, Dual Mode or Switch device.
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Allows the DesignWare PCI Express port logic to bridge to the AMBA 2.0 AHB on-chip bus
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Allows the DesignWare PCI Express port logic to bridge to the AMBA AXI3/AXI4 on-chip bus
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Integrates quickly and easily into SoC designs with a user-friendly application interface and conservative timing suitable for a wide range of ASIC and FPGA technologies
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  • 1.1 PHY
  • Low power, small area PCI Express 1.1 PHY operating at 2.5 Gbpsmore

 
The low power PHY integrates high-speed mixed-signal custom CMOS circuitry The IP is compliant with the PCIe 1.1 specification and PIPE interface standard.
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  • 2.1 PHY
  • High performance, low power PCI Express 2.1 PHY operating at 5.0 Gbpsmore

 
The low power PHY integrates high-speed mixed-signal custom CMOS circuitry. The IP is compliant with the PCIe 2.0 specification and PIPE interface standard
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  • 3.0 PHY
  • Multi-channel, low power PCI Express 3.0 PHY operating at 8.0 Gbpsmore

 
Compliant with the PCI Express 3.0 (8.0 GT/s), 2.0 (5.0 GT/s) and 1.1 (2.5 GT/s) specifications
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Verifies PCI Express endpoints, switch and root complex devices. The IP can be configured for verification at multiple levels including the 8b/10b and PIPE.
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Digital Core IP
  • Broad portfolio including Endpoint, Dual Mode, Root Port, & Switch/Bridge
  • Silicon proven; low latency and low gate count
  • Powers the Agilent and PCI-SIG protocol test card
  • Largest installed base of all PCI Express IP providers
PHY IP
  • Designed for integration of both upstream and downstream applications as well as PCI Express bridges and switches
  • Fully compliant with the PCI Express 3.0 (8 GT/s), 2.x (5.0 GT/s), and 1.x (2.5 GT/s) as well as the PHY interface for PCIe 3.0 (PIPE4 draft 6) (8-bit, 16-bit and 32-bit) specifications
  • Multi-tap adaptive continuous time linear equalizer (CTLE) and decision feedback equalization (DFE)
  • Extremely low in power consumption and size for smaller die area, improved jitter and sensitivity
Verification IP
  • Verifies all configurations of the digital core including PCI Express endpoints, switches and root complex devices
  • Supports directed and constrained random traffic generation
  • Provides functional coverage of PCI Express transactions and coverage of the PCI Express compliance checklist


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