DesignWare Interface and Standards IP 

Complete, Interface IP Solutions for the Most Popular Protocols 

Synopsys offers designers a broad portfolio of complete, silicon-proven IP solutions for the most widely used interfaces such as PCI Express, USB, DDR, SATA, HDMI, MIPI, and Ethernet. With a strong investment in developing high quality IP, designers can trust that the IP will interoperate and integrate successfully into the SoC with less risk and improved time to market.

Thousands of customers trust DesignWare IP in their SoCs. See why Synopsys is their Trusted IP Partner.

  • Products
 
  • AMBA
  • Comprehensive IP solutions for AMBA 2.0, AMBA 3 AXI and AMBA 4 AXImore

Infrastructure/Fabric
The DesignWare IP solutions for the AMBA® interconnect includes synthesizable IP, verification IP and an automated method for subsystem assembly.


DMA Controller
The highly optimized centralized DMA Controller supports up to 8 channels each with dedicated channel buffers.


DDR/SDRAM/SRAM Memory Controller
The multi-purpose memory controller supports a wide variety of standard memory devices and provides flexible configuration options.


APB General Peripheral
The highly configurable APB general peripherals provide designers with the flexibility to tailor the components to the desired design requirements.


APB Advanced Peripheral
The highly configurable APB Advanced Peripheral provide designers with the flexibility to tailor the components to their desired design requirements


Verification IP
AMBA VIP includes support for AMBA AXI4, ACE, AXI3 AHB and APB. It is based on Synopsys’ SystemVerilog UVM architecture and supports all popular simulators.

  • DDR
  • Complete DDR4/3/2 and LPDDR4/3/2 IP solutions for up to 3200 Mbps more

DDR Complete Solution
Complete DDR IP solution consisting of protocol and memory controllers, PHY IP, and Verification IP
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Enhanced Universal DDR Controllers
DDR memory and protocol controller IP supporting DDR4, DDR3/3L/3U, DDR2, Mobile DDR, LPDDR4, LPDDR3, and LPDDR2
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Universal DDR Controllers
DDR memory and protocol controller IP supporting DDR3/3L/3U, DDR2, Mobile DDR, LPDDR, and LPDDR2
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DDR4 multiPHY
Supports DDR4 and DDR3/3L/3U up to 2667 Mbps and LPDDR3/2 up to 2133  Mbps
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LPDDR4 multiPHY
Supports LPDDR4, LPDDR3, DDR4, DDR3/3L/3U SDRAMs up to 3200 Mbps
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Gen 2 DDR multiPHY
Supports LPDDR3/2 up to 2133 Mbps and DDR3/3L/3U up to 2133 Mbps
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DDR multiPHY
Supports LPDDR2, Mobile DDR, DDR3/3L/3U, and DDR2 up to 1066 Mbps
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DDR3/2 SDRAM PHY
Supports DDR3/3L and DDR2 up to 2133 Mbps
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DDR2/3-Lite/mDDR SDRAM PHY
Supports DDR3, DDR2 and LPDDR up to 1066 Mbps
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  • Ethernet
  • Comprehensive Ethernet 10/100/1G/10G/40G Solutionsmore

Ethernet Complete Solution
Complete Ethernet IP solution including digital cores, PHY IP and verification IP.
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Enterprise 12G PHY
1.25-12.5G PHY for 40GBASE-KR4, 10GBASE-KR, 10GBASE-KX4 (XAUI), 1000BASE-KX, 40GBASE-CR4, CEI-6G, CEI-11G, SGMII, QSGMII, XFI, and SFI (SFF-8431)


Enterprise 10G PHY
Multi-channel, multi-protocol PHY IP compliant with IEEE 802.3 10GBASE-KR, 40GBASE-KR4, CEI-6G, SGMII, and QSGMII


Enterprise 40G MAC
High-performance, energy-efficient Ethernet MAC IP compliant with IEEE 802.3-2012 specification including IEEE 802.3ba standard for 40G Ethernet host applications


Enterprise 40G PCS
High-performance, energy-efficient Ethernet PCS IP compliant with IEEE 802.3-2012 and IEEE 802.3ba standard for 40G Ethernet applications


Ethernet Quality-of-Service
Compliant with the IEEE 802.3 standard and supports the IEEE 1588-2002, IEEE 1588-2008 and IEEE AVB specifications


10/100/1G
Compliant with IEEE 802.3, 802.1Q, and 1588-2002 specifications with checksum engine offload engine and AMD Magic packet support.
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10/100
Compliant with IEEE 802.3, 802.1Q, and 1588-2002 specifications with checksum engine offload engine and AMD Magic packet support.
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1G/2.5G/10G
Compliant with the IEEE 802.3ae, IEEE 802.3x with configurable RMON/MIB counters and an optional MDIO interface as part of a full 10G solution.
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Ethernet PCS
Implements the PCS layer of the 10 Gigabit Ethernet Extended Sub-layer (XGXS) as described in the IEEE 802.3ae specification.<
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XAUI PHY
XAUI PHY supports the 10G Ethernet standards (IEEE 802.3ae specification) in a wide range of process technology nodes


Verification IP
Ethernet VIP supports speeds from 10/100M up to 100G for verification of MAC and PHY interfaces. Based on Synopsys’ SystemVerilog UVM architecture and supports all popular simulators.
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  • HDMI
  • Silicon-proven HDMI 2.0, 1.4 and 1.3 TX & RX solution: Controller and PHYmore

HDMI 2.0 Transmitter (TX)
The HDMI 2.0 TX interface comprises Controller IP, PHY IP, software, and Linux drivers to perform the serialization and transmission of audio, video, and control information.
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HDMI 2.0 Receiver (RX)
The HDMI 2.0 RX interface comprises Controller IP, PHY IP, software, and Linux drivers to perform the serialization and reception of audio, video, and control information.
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HDMI 1.4 Transmitter (TX)
The HDMI 1.4 TX interface comprises of Controller and PHY to perform the serialization and transmission of video, audio and control information through and HDMI interface.
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HDMI 1.4 Receiver (RX)
The HDMI 1.4 RX interface compromises of Controller and PHY to perform the serialization and transmission of video, audio and control information through an HDMI interface.
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HDMI 1.3 Transmitter (TX)
The HDMI 1.3 TX interface comprises of Controller and PHY to perform the serialization and transmission of video, audio and control information through an HDMI interface.
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HDMI 1.3 Receiver (RX)
The HDMI 1.3 RX interface comprises of Controller and PHY to perform the serialization and transmission of video, audio and control information through an HDMI interface.
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Verification IP
HDMI VIP includes support for HDMI 1.3a, 1.4a. 1.4b, 2.0 and HDCP. It is based on Synopsys’ SystemVerilog UVM architecture and supports all popular simulators
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  • JPEG
  • Multimedia IP solution for image compression and decompressionmore

 
The CODEC encodes and decodes still or motion image data of up to four color components, according to the JPEG baseline algorithm as specified in the ISO/IEC 10918-1 standard.
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  • MIPI
  • PHY and controller IP solutions for the MIPI interfacemore

MIPI Complete Solutions
Complete solutions that include digital controllers and PHY IP including multi-gear M-PHY, UFS Host Controller, UniPro Controller, D-PHY, DigRF v4 and 3G, CSI-2, DSI and VIP
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M-PHY
Scalable, low-power, low-latency and compact footprint solution supporting LLI, SSIC, DigRFv4, UniPro, UFS and DSI-2 protocols
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UniPro
Compliant with MIPI UniPro v 1.41 and supports all host and device configurations for JEDEC UFS, MIPI CSI-3, and MIPI DSI-2
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UFS Host
Mobile storage serial interface compliant with the JEDEC UFS Architecture Specification (UFS) and the JEDEC UFSHCI
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DigRF v4
Area, power, and pin count efficient interface for advanced LTE and Mobile WiMax Baseband SoCs and RFICs
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DigRF 3G
Controllers and PHYs for MIPI DigRF V3 standard interface for Baseband and RFICs targeting dual-mode 2.5G / 3G mobile phone systems
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D-PHY
Physical Layer for MIPI CSI-2, DSI and UniPro standard interfaces with up to 4 lanes serial interface available in advanced technology nodes
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CSI-2
Synthesizable controller for MIPI CSI-2 host application, compliant to MIPI CSI-2 specification rev 1.0
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DSI
Synthesizable controller for MIPI DSI host application, compliant to the DSI specification rev 1.01
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CSI-2 Verification IP
CSI-2 VIP can act as a transmitter or receiver and supports high speed and ultra low power. It is based on Synopsys’ SystemVerilog UVM architecture and supports all popular simulators.
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DigRFv4 Verification IP
DigRFv4 VIP acts as a transmitter or receiver and includes support for M-PHY and RMMI interfaces. Based on Synopsys’ SystemVerilog UVM architecture and supports all popular simulators.
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DSI Verification IP
DSI VIP acts as a transmitter or receiver and supports for high speed and ultra low power. Based on Synopsys’ SystemVerilog UVM architecture and supports all popular simulators.
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M-PHY Verification IP
M-PHY VIP supports M-PHY version 2.0 and supports the serial and RMMI interfaces. It is based on Synopsys’ SystemVerilog UVM architecture and supports all popular simulators.
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Supports the SD 2.00, SDIO 1.1, MMC 4.2 and CE-ATA 1.1 specification. The IP is optimized for low power, high performance storage devices
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  • PCI Express
  • Complete, silicon-proven PCI Express 4.0, 3.1, 2.1, and 1.1 IP solutionsmore

PCIe Complete Solution
Complete PCIe IP solution consisting of digital controllers, PHY IP, and Verification IP for PCIe 4.0, 3.1, 2.1, and 1.1.
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Endpoint
Implements the port logic required for a PCIe Endpoint and is compliant with the PCI Express 4.0, 3.1, 2.1, 1.1, and PCI-SIG SR-IOV specifications.
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Root Port
Implements the port logic required for a PCIe Root Complex and is compliant with the PCI Express 4.0, 3.1, 2.1, and 1.1 specifications.
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Dual Mode
Implements the port logic required for both a PCIe Root Complex and Endpoint and is compliant with the PCIe 4.0, 3.1, 2.1, 1.1, and PCI-SIG SR-IOV specifications.
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Switch Port
Implements the upstream or downstream port logic required for a PCIe Switch or Bridge and is compliant with the PCI Express 4.0, 3.1, 2.1, and 1.1 specifications.
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M-PCIe
Scalable controller IP implementing port logic required to build a root Port, Endpoint, Dual Mode, or Switch device compliant with the PCIe 3.0 specification and the M-PCIe ECN.
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PCIe to AHB Bridge
Allows the DesignWare PCI Express port logic to bridge to the AMBA 2.0 AHB on-chip bus.
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PCIe to AXI Bridge
Allows the DesignWare PCI Express port logic to bridge to the AMBA 3 AXI on-chip bus.
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1.1 PHY
The low power PHY integrates high-speed mixed-signal custom CMOS circuitry The IP is compliant with the PCIe 1.1 specification and PIPE interface standard.
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2.1 PHY
High-performance, low-power PCI Express 2.1 PHY operating at 5.0 Gbps


3.1 PHY
Multi-channel, low active and standby power PCI Express 3.1 PHY operating at 8.0 Gbps with L1 sub-state and SRIS support. Compliant with the PCI Express 3.1 (8.0 Gbps), 2.0 (5.0 Gbps),1.1 (2.5 Gbps), and PIPE 4.2 specifications.


4.0 PHY
Multi-channel, low active and standby power PCI Express 4.0 PHY operating at 16.0 Gbps with L1 sub-state and SRIS support.


Verification IP
PCIe VIP acts as either a RC or endpoint and supports Gen1, Gen2 and Gen3 speeds. It includes support for PIPE, PCS/PMA or SERDES interfaces and supports all popular simulators.
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PCI
The PCI IP supports 32-bit or 64-bit bus paths on either the PCI bus or the application interface and is compliant with the PCI 2.3 specification.
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PCI-X
The IP supports 32-bit or 64-bit PCI-X bus paths and is compliant with the PCI-X 2.0 (mode1) also know as 1.0a and the PCI 2.3 specifications.
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  • SATA
  • Complete, interoperable SATA IP Solution: Device, Host, PHY, VIPmore

SATA Complete Solution
Comprehensive SATA IP solution consisting of host, device, PHY and Verification IP.
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SATA PHY
Low in power consumption and area, the PHY substantially exceeds the electrical specifications in such key performance areas as jitter and receive sensitivity
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Verification IP
Synopsys SATA VIP can act as a device or a host and includes support for SATA Gen1, Gen2 and Gen3 with speeds up to 6GB. It supports all popular simulators.
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  • USB
  • Complete, silicon-proven USB IP solution: controller, PHY and VIPmore

USB Complete Solution
Complete USB IP solution including controllers, PHY IP, Verification IP, drivers, and IP prototypes for SuperSpeed USB 3.0, SSIC, HSIC, USB 2.0, LPM-HSIC and more
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USB 3.0 Dual-Role Device
USB 3.0-compliant IP for Device- and Host-side applications. Supports SuperSpeed, High-Speed, Full Speed and Low Speed implementations as well as SSIC, HSIC and OTG


USB 3.0 xHCI Host
USB 3.0-compliant IP for Host-side applications. Supports SuperSpeed, High Speed, Full Speed and Low Speed implementations as well as SSIC and HSIC


USB 3.0 Device
USB 3.0-compliant IP for Device-side applications. Supports SuperSpeed and High-Speed implementations as well as SSIC and HSIC


USB 3.0 PHY IP
Compliant USB 3.0 PHY IP for SoC integration in Device and Host applications


USB 3.0 femtoPHY
Supports complete USB 3.0 implementation (SuperSpeed, High Speed, Full Speed, and Low Speed) in a 50% smaller footprint than the standard USB 3.0 PHY
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USB 2.0 HS OTG
The IP performs as a standard Hi-Speed Dual-Role Device (DRD), operating as either a USB 2.0 compliant peripheral or a USB 2.0 host
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USB 2.0 EHCI Host
Compliant with the specifications for the USB 2.0 Enhanced Host Controller Interface (EHCI) and the USB 1.1 Open Host Controller Interface (OHCI) 1.0
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USB 2.0 Device
Compliant to the USB 2.0 specification. The IP supports high-speed (480-Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) devices and USB 2.0 UTMI
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USB 2.0 PHY
Compliant USB 2.0 PHY IP for SoC integration in Device and Host applications


USB 2.0 femtoPHY
Supports complete USB 2.0 implementation (High Speed, Full Speed, and Low Speed) in a 50% smaller footprint than the standard USB 2.0 PHY.
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USB 2.0 picoPHY
The USB 2.0 picoPHY supports the Battery Charging v1.1 and OTG 2.0 specifications, and is designed for low power and small area
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USB 2.0 nanoPHY
Compliant to the USB 2.0 specification. The USB 2.0 nanoPHY is targeted to leading 45nm, 55nm, and 65nm low power digital logic processes
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USB 2.0 LPM-HSIC PHY
Compliant to the USB 2.0 specification. The IP supports 1.2V LVCMOS signaling with integrated PHY including transmitter, receiver, digital core, ESD & 480 Hz PLL
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USB 1.1 Host
The USB 1.1 Host is compliant with the USB 1.1 specification. The IP supports full and low speeds and is compatible with USB 2.0 & Open HCI 1.0 specifications.
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USB 1.1 Device
The USB 1.1 Device is compliant with USB 1.1 specification. The IP supports full and low speeds devices.


USB 1.1 Hub
The USB 1.1 Hub is compliant with USB 1.1 specification. The IP supports low-speed and full speed devices on downstream ports
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Verification IP
USB 3.0 VIP supports USB 3.0, 2.0 and OTG. It can act as a host, device or hub. It is based on Synopsys' SystemVerilog UVM architecture and supports all popular simulators.
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