IP-SoC 2013 Conference and Exhibition is the only international event fully dedicated to IP in electronics systems, including interface, analog and processor IP. The event includes information on IP best practices, design, quality and verification, system architecture, and more.
This year’s event will feature multiple presentations by Synopsys as well as demonstrating DesignWare® IP for M-PCIe in the exhibit hall.November 6-7, 2013World Trade Center, 5 place Robert Schuman, 38 000 Grenoble, FranceSynopsys Highlights at IP-SoC 2013
Synopsys Booth #12
- Keynote: Virtual Prototyping - A Reality Check
Virtual prototypes have been used by the semiconductor and software development industry for many years, but still there are many different perspectives on the merits and efforts around virtual prototyping. This talk will highlight current industry practice around putting virtual prototyping to work for early software development, with specific emphasis on the value chain for the creation and use of virtual prototypes.
- Moving PCI Express to Mobile (M-PCIe)
This presentation will begin with an overview of the M-PCIe specification and its application space, and then go into details such as bandwidth and clocking considerations, PHY interface differences, power management impacts, and the tradeoffs related to choices around link-layer changes.
- Scalable Architectures for Analog IP on Advanced Process Nodes
This presentation compares the attributes of common analog-to-digital converter (ADC) architectures, including the Successive Approximation Register (SAR)-based architecture, for use in medium- and high-speed 28-nm ADCs. It describes advantages of the SAR-based architecture that reduce power consumption and area usage for mobile and multimedia SoCs. Finally, it presents the DesignWare SAR-based ADC family for 28-nm and explains how it benefits from advanced process nodes through adherence to the area and power scaling paradigms of digital circuitry.
- Low-Power Analysis and Verification of USB Super Speed Inter-Chip (SSIC) IP
This presentation focuses on low power analysis and verification challenges of SoC designers using USB 3.0 SSIC IP. Accurate verification demonstrates the IP’s functionality before, during and after the SSIC power gating feature, called hibernation. The paper highlights a low-power analysis that showcases the power savings achieved in DesignWare SSIC IP with and without use of the hibernation state.
- DesignWare IP for M-PCIe Interoperability Demonstration
The new M-PCIe ECN was designed to support the needs of very low-power PCI Express devices while maintaining the benefits of the PCI Express protocol. The DesignWare Controller IP for M-PCIe leverages the market-leading DesignWare Controller IP for PCIe 3.0 to provide designers with a full implementation of the M-PCIe ECN. This demonstration showcases the DesignWare IP for M-PCIe and the DesignWare MIPI HS-Gear3 M-PHY interoperating with a leading semiconductor company’s M-PCIe solution. View a preview of the demonstration.
For more information or to register, go to IP-SOC 2013 Conference and Exhibition.