Low power management is a critical design challenge for many of today's systems-on-chips (SoC). Engineers are often faced with the challenge of creating complex SoCs with increased amounts of functionality while maintaining or decreasing power consumption. Adopting reusable IP has become a common practice to help cope with the increased design complexity while maintaining time to market schedules. With this mind, designers who are implementing a chip level power strategy must now taking into consideration the IP vendor's ability to provide IP that is designed with low power techniques and can be easily integrated into the chip.
As a leader in low power IP, DesignWare® IP supports a wide range of low power features such as configurable shutdown and power modes. An integral part of the Synopsys Low Power Solution, the DesignWare digital IP is designed to support low power methodologies and the PHY IP consumes up to 50% less power than the competition. As a leading IP provider, Synopsys offers a broad portfolio of IP that is low power by design.
DesignWare minPower Components
Today’s conventional techniques do not address reducing specific power elements such as glitch power in deep logic levels and dynamic power in high-performance datapath pipelines. The DesignWare minPower Components offer unique, power-optimized datapath architectures that enable DC Ultra™ to automatically generate circuits that suppress switching activity and glitches, reducing both dynamic and leakage power for mobile devices and high-performance applications. Based on the actual switching activities, transition probabilities, available standard cells and analysis of possible configurations, the DesignWare minPower Components architectures are automatically configured by DC Ultra to implement the optimal structure with the lowest power consumption. In addition to the automatically inferable components, the DesignWare minPower Components also include more than 40 instantiable blocks that incorporate low power design techniques such as enhanced clock gating, built-in datapath gating and patented data-tracking pipeline management technology to reduce power consumption.
DesignWare PHY IP
Synopsys' comprehensive portfolio of high performance, low power mixed-signal PHY IP for the PCI Express, SATA, XAUI and USB protocols, enable designers to quickly integrate high performance interfaces into their next-generation SoCs while minimizing power consumption. Designed with low power in mind, all of the DesignWare PHY IP is built with a high performance architecture that provides low area and up to half the power compared to competitive solutions.
The Synopsys DesignWare USB IP now provides support for the USB 2.0 Link Power Management (LPM) and High Speed Inter-Chip (HSIC) standards. The DesignWare USB LPM and HSIC IP reduces power consumption and area for USB-enabled designs. LPM defines a new sleep state to provide faster suspend and resume times and HSIC eliminates the USB connectors and cables, thus simplifying the USB connection down to two wires.
DesignWare Digital IP and Foundry Libraries
Synopsys' DesignWare digital IP portfolio support a wide range of protocols such as PCI Express®, USB and DDR. The low power digital IP when combined with the PHY IP and Verification IP provide designers with an integrated, complete IP solution. The DesignWare digital IP leverages Synopsys. low power design tools and methodology to enable more power efficient integrated circuits. Maximum extent of the digital cores can be clock gated to reduce power. In addition, it also supports low power management schemes specified by the protocol standards.
- Low Power Design for Analog/Mixed-Signal IP
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