Designers are often faced with the challenge of creating complex SoCs with increased amounts of functionality while lowering power consumption. Synopsys DesignWare® IP supports a wide range of low power features and implements the latest advanced low power techniques.
The DesignWare Interface IP portfolio supports a wide range of protocols such as USB, PCI Express®, DDR, MIPI, HDMI and SATA. Specific IP implements key power management features including multiple power rails, hibernation, power-down retention, USB battery charging, PCI Express L1 sub-states along with power gating techniques including the utilization of power switches, power islands or retention cells.
Embedded Memories and Logic Libraries
The DesignWare Duet Packages of Embedded Memories and Logic Libraries include memory compilers, ROMs, standard cells, Power Optimization Kits (POKs) and optional overdrive/low voltage PVTs to deliver the maximum performance with the lowest possible power consumption. The HPC Design Kit contains high-speed and high-density memory instances and logic cells that enable SoC designers to optimize their CPU, GPU and DSP cores for maximum speed, smallest area, lowest power or an optimum balance of all three.
ARC 32-bit processors are optimized to deliver the best performance/power/area (PPA) efficiency for embedded SoCs. The processors' extensible instruction set gives designers the ability to define their own custom instructions to dramatically improve application-specific performance, while reducing power consumption and memory requirements. In addition, the ARC processors are highly configurable, enabling designers to tailor them to meet the PPA requirements of each target application. Synopsys also offers the DesignWare EV Family of processors, which is specifically optimized to meet the demanding power and performance requirements of embedded vision applications.
Sensor and Control IP Subsystem
Synopsys' pre-validated, hardware and software DesignWare Sensor and Control IP subsystem is optimized to process data from digital and analog sensors, offloading the host processor and enabling more power efficient processing of the sensor data. The subsystem is as small as 0.1mm2 with significant cycle count reduction.
The DesignWare Analog IP implements extensive low-power design techniques and digitally assisted analog architectures to reduce IP power dissipation by up to 5X compared to the previous generation. Power dissipation is reduced in active, shut-off, and idle operations, making the analog IP ideal for power-sensitive applications, including battery-powered mobile and wearable devices.
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