DesignWare IP White Papers 

Developing High-Reliability Reprogrammable NVM IP for Automotive Applications
To help IC designers understand the complexities in developing the highest reliability non-volatile memory (NVM) IP for automotive applications, this white paper will review key considerations from design to test, including: key reliability specifications, designing-in reliability, and demonstrating reliability through characterization, qualification, and reliability testing. This paper helps IC designers make informed choices for their automotive designs, from developing the NVM IP in-house to selecting the optimal IP supplier.
Martin Niset, Senior Engineering Manager, Synopsys, Inc.; Craig Zajac, Senior Product Marketing Manager, Synopsys, Inc.

Designing ASIPs in Multicore SoCs
Modern SoCs integrate dozens of complex system functions, each requiring its own optimal balance of performance, flexibility, energy consumption, communication, and design time. The traditional model of a (configurable) general-purpose processor core with a number of fixed hardware accelerators no longer suffices. Application-specific instruction-set processors (ASIPs) can offer the best balance for each system function, and thus form the basis of new generations of multicore SoCs. ASIP design requires tools and methodologies that enable fast architectural exploration, hardware synthesis, software compilation, inter-ASIP communication, and verification. Any ASIP design approach has to support a broad range of architectures, from small microprocessors, over DSP dominated cores, to VLIW and vector processors.
Gert Goossens, R&D Director; Dirk Lanneer, R&D Manager; Werner Geurts, CAE Manager; Johan Van Praet, R&D Manager, Synopsys

Building an Efficient, Tightly Coupled Embedded System Using an Extensible Processor
The increasing demand for better filtering and processing capabilities of the processor within embedded systems results in a trend to shift from 8-bit microcontroller tightly coupled embedded systems towards 32-bit processor bus-based embedded systems, which has caused the power, performance and area (PPA) ratio of these systems to also shift in favor of performance at the cost of power and area. Closely coupled memories, together with ARC Processor EXtension (APEX) technology, provide a means to tightly couple memories and peripherals to an ARC processor core and make the area- and latency-expensive bus infrastructure redundant, reducing both the power consumption and area costs of the embedded system without sacrificing performance.
Jeroen Geuzebroek, Sr. R&D Engineer, Synopsys; Ad Vaassen, Sr. System Engineer, Synopsys

Ultra Low-Power 9D Sensor Fusion Implementation
Today, the ability to track the orientation or position of a device is a common feature in many portable and wearable products. Computing the orientation is a non-trivial task that converts inputs from multiple motion sensors into accurate position information. This computation is called sensor fusion and it eliminates inaccuracies from noisy sensor inputs. This paper shows how using ARC Processor EXtension (APEX) technology improves cycle count and energy consumption for a power-efficient implementation of a 9D fusion algorithm on an IP subsystem.
Pieter Struik, R&D Engineer, Sr. Staff, Synopsys

Leveraging Processor Extensibility to Build an Ultra Low-Power Embedded Subsystem
The ever increasing demand for smaller electronic devices, with more functionality, longer battery life, and shorter time to market has accelerated use of embedded processors and subsystems to offload the host processor from commonly executed tasks. Processor extensions provide a means to extend a general-purpose processor with custom hardware accelerators to optimize the execution of dedicated applications for reduced energy consumption and area, and/or increased performance. This white paper describes how processor extensions can optimize power and performance of a processor when targeting sensor applications, demonstrated using Synopsys’ DesignWare® ARC® Processors and ARC Processor Extensions (APEX) technology.
Jeroen Geuzebroek, Senior R&D Engineer, Synopsys

USB 3.1: Evolution and Revolution
USB-IF Worldwide Developers Days introduced developers to the new USB 3.1 specification. On the surface, USB 3.1 seems like it could be only an update to 10G speeds, but this white paper will dig deeper into 10G USB 3.1 to clarify the evolutionary and revolutionary changes in the USB 3.1 specification. USB 3.1 introduces a new 10 Gbps signaling rate in addition to the 5 Gbps signaling rate defined in the USB 3.0 specification.
Morten Christiansen, Technical Marketing Manager, USB IP, Synopsys; Eric Huang, Product Marketing Manager, USB IP, Synopsys

The Linley Group: Synopsys ARC HS Processors: High-Speed Licensable CPU Cores for Embedded Applications
This white paper describes the Synopsys DesignWare® ARC® HS (High Speed) processor family. ARC HS34 and HS36 are the first members of the company’s newest family of licensable CPU cores for embedded applications that need 32-bit RISC performance in a small silicon footprint with minimal power consumption. The Linley Group prepared this report after evaluating ARC HS performance data and technical features.
Tom R. Halfhill, Senior Analyst, The Linley Group; J. Scott Gardner, Senior Analyst, The Linley Group



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