DesignWare IP White Papers 

Meeting the USB IP Requirements of SoC Designs from 180-nm to 14/16-nm FinFET
USB’s ease-of-use and wide availability is belied by USB IP designers’ technical innovations. Without these innovations, USB could not be enabled in a broad range of process technologies ranging from 180-nm to the latest 14/16-nm FinFET technologies. This white paper addresses the five critical challenges facing designers of USB IP who need to keep pace with the process technology changes as well as the USB standard evolution.
Gervais Fong, Sr. USB Product Marketing Manager, Synopsys

How VXLAN-Based Ethernet IP Solves Cloud Computing Network Bottlenecks
Network virtualization technologies running over optimized Ethernet IP are enabling cloud computing data centers to expand and support the growing amount of internet traffic. Hyperscale cloud data centers are driving requirements for new network overlay protocols such as Virtual Extensible LAN (VXLAN) running over Ethernet. This whitepaper discusses in detail the benefits of VXLAN and how it can be used to overcome network subnet limits as well as the impact of VXLAN to Ethernet IP implementations. It will also describe how IP supporting VXLAN enables a new class of SoCs optimized for next-generation network virtualization.
Ron DIGiuseppe, Sr. Strategic Marketing Manager, Synopsys

Reliability, Availability and Serviceability (RAS) for Memory Interfaces
Smaller process geometries and higher Double Data Rate (DDR) Dynamic Random Access Memory (DRAM) interface speeds are driving demand for new and more robust techniques for preventing, repairing and detecting memory errors. Some of these techniques are enabled by features in the latest DDR4 and DDR3 RDIMM standards, and others can be applied to any DRAM type. Collectively these techniques improve the Reliability, Availability, and Serviceability (RAS) of the computing system that adopts them. This white paper reviews some of the ways that errors can occur in the DDR DRAM memory subsystem and discusses current and future methods of improving RAS in the presence of these errors.
Marc Greenberg, Product Marketing Director, DDR Controllers, Synopsys, Inc.

Developing High-Reliability Reprogrammable NVM IP for Automotive Applications
To help IC designers understand the complexities in developing the highest reliability non-volatile memory (NVM) IP for automotive applications, this white paper will review key considerations from design to test, including: key reliability specifications, designing-in reliability, and demonstrating reliability through characterization, qualification, and reliability testing. This paper helps IC designers make informed choices for their automotive designs, from developing the NVM IP in-house to selecting the optimal IP supplier.
Martin Niset, Senior Engineering Manager, Synopsys, Inc.; Craig Zajac, Senior Product Marketing Manager, Synopsys, Inc.

Building an Efficient, Tightly Coupled Embedded System Using an Extensible Processor
The increasing demand for better filtering and processing capabilities of the processor within embedded systems results in a trend to shift from 8-bit microcontroller tightly coupled embedded systems towards 32-bit processor bus-based embedded systems, which has caused the power, performance and area (PPA) ratio of these systems to also shift in favor of performance at the cost of power and area. Closely coupled memories, together with ARC Processor EXtension (APEX) technology, provide a means to tightly couple memories and peripherals to an ARC processor core and make the area- and latency-expensive bus infrastructure redundant, reducing both the power consumption and area costs of the embedded system without sacrificing performance.
Jeroen Geuzebroek, Sr. R&D Engineer, Synopsys; Ad Vaassen, Sr. System Engineer, Synopsys



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