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Synopsys ARC 700 Processor Core Family
ARC Processors Everywhere
Industry's best performance efficiency for embedded
The Synopsys ARC 700 family includes the ARC 710D, ARC 725D and ARC 770D processors, which are highly configurable so that each instance can be tailored to achieve the optimum balance of performance, power and area, enabling SoC designers to optimize the processors for their specific target applications. The ARC 700 processors are also extensible, allowing designers to add their own custom instructions to dramatically increase performance.
Optional DSP and floating point unit (FPU) capabilities enable designers to address a wide range of processing requirements with a single host application processor. Using a single processor simplifies the design, lowers silicon-area and enables faster debug of the chip.
Synopsys ARC processor cores are supported by a variety of 3rd-party tools, operating systems and middleware from leading industry vendors, including members of the ARC Access Program.
PPA Efficiency
The ARC Advantage: Maximum Performance With Minimum Area and Power
ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
Configurability
The ARC Advantage: Implement Only the Hardware You Need to Optimize PPA
ARC processors are highly configurable, allowing designers to optimize the performance, power and area of each processor instance on their SoC by implementing only the hardware needed. The ARChitect wizard enables drag-and-drop configuration of the core, including options for
- Instruction, program counter and loop counter widths
- Register file size
- Timers, reset and interrupts
- Byte ordering
- Memory type, size, partitioning, base address
- Power management, clock gating
- Ports and bus protocol
- Multipliers, dividers and other hardware features
- Licensable components such as a Memory Protection Unit (MPU), Floating Point Unit (FPU) and Real-Time Trace (RTT)
- Adding/removing instructions
Extensibility
The ARC Advantage: Add User-Defined Instructions to Accelerate Code Execution and Lower Power Consumption
ARC Processor EXtension (APEX) technology enables ARC users to easily add their own custom hardware to the processor, dramatically boosting performance and/or reducing power consumption for their targeted application(s). ARC processors can be extended with:
- User-defined instructions
- User-supplied hardware (e.g., Verilog RTL)
- Core registers
- Auxiliary registers
- Condition & status codes
- Memory mapped blocks and closely coupled peripherals
ARC processor extensions enable users to dramatically improve performance, power and area. User-defined instructions, for example, can accelerate software execution, enabling the same code to run in much fewer cycles which reduces energy consumption by lowering clock frequency requirements (or enables the execution of more operations with the same energy.) Code size is also reduced, lowering memory requirements which leads to additional cost and power savings.
The APEX interface also enables ARC users to tightly couple memory and peripherals to the processor, eliminating the need for additional bus infrastructure. The resulting "bus-less" design further reduces area and latency, increasing system-level performance while reducing costs.
