DesignWare IP White Papers 

Three Power Saving Techniques Using PCI Express IP
The increasing data traffic between devices in a computing application environment is causing a large power footprint and for that reason designers are looking for ways to lower the power consumption of their SoCs during sparse or idle times. The smaller, battery-powered devices are often idle and in deep sleep modes, but these deep power saving modes come at the cost of slow resume times to switch back to normal operating mode. This paper uses PCI Express IP as an example to describe three power saving techniques and how designers are using the protocol’s and design tools’ power management features to deliver power-efficient SoCs for devices requiring fast resume times.
Athul Sripad, ASIC Digital Design Engineer, Synopsys

High Performance and Scalable Sensor Connectivity with MIPI I3C
The MIPI® Alliance is working on a new standard called I3C (or SenseWire) that incorporates and unifies key attributes of I2C and Serial Peripheral Interface (SPI). MIPI I3C enhances the capabilities and performance of each approach with a comprehensive, low pin count and scalable interface as well as architecture. It supports sensor interface architectures that mobile, mobile-influenced, and embedded-system applications anticipate to require in the near future. This paper describes the MIPI I3C specification and its key benefits for a seamless transition from I2C to I3C.
Sriram Balasubramanian, Sr. Manager, IP R&D, Synopsys; Hezi Saar, Staff Product Marketing Manager, Synopsys

Securing the Internet of Things Using Hardware Rooted Processor Security - An Architect’s Guide
Security is a key requirement for Internet of Things (IoT) devices and must be considered for all aspects of the design. This paper provides an overview of security basics, feature requirements, technical solutions, and associated system-level trade-offs for implementing security in IoT devices. Making the required trade-offs is significantly easier by leveraging secure, proven building blocks that were designed with secure systems in mind and optimized for low footprint and energy. This paper can help you decide on the optimal mix of features and best tradeoffs to make for your specific IoT device that will result in a secure architecture that can be efficiently implemented.
Ruud Derwig, Senior Staff Engineer, Synopsys

Foundation IP for 7nm FinFETs: Design and Implementation
Learn about the challenges of IP design and implementation for 7nm FinFETs. Along with the performance and area benefits that the node brings, designers must understand the significant technical challenges stemming from increasing variability associated with tighter pitches and more complex lithography steps. Design for variability and reliability considerations will require comprehensive modeling and analysis as well as advanced circuit techniques such as on chip sensing and compensation.
Jamil Kawa, Synopsys Fellow, Synopsys

Optimizing LPDDR4 Performance and Power with Multi-Channel Architectures
LPDDR4 offers huge bandwidth in a physically small PCB area and volume; up to 25.6 GByte/s of bandwidth at a 3,200 Mbps data rate from a single 15mmx15mm LPDDR4 package when two dies are packaged together. LPDDR4 builds on the success of LPDDR2 and LPDDR3 by adding new features and introducing a major architectural change. This white paper discusses why designers are selecting LPDDR4, how to handle 2-die and 4-die packages with multi-channel connections, the advantages of sharing channels through system-on-chip (SoC) partitioning, and how to optimize channels for the lowest power consumption.
Marc Greenberg, Director of Product Marketing for DDR IP, Synopsys

Addressing Three Critical Challenges of USB Type-C Implementation
As designers create new products and system-on-chips (SoCs) with USB Type-C support, they need to be aware of partitioning challenges. The SoC and system design must be partitioned to support the specification’s requirements for precision analog circuitry plus high voltage/high current switches, and Type-C management software must be partitioned to execute on the processor, internal microcontroller, microcontroller in a power management IC, and/or on an external dedicated USB Type-C chip. This white paper describes key challenges and suggests solutions for designers of USB Type-C products and SoCs with native USB Type-C support.
Morten Christiansen, Technical Marketing Manager, USB, Synopsys

Designing an Efficient DSP Solution: Choosing the Right Processor and Software Development Toolchain
Read about key challenges in DSP implementation from both hardware and software application perspectives, and learn how a properly selected and configured DSP processor coupled with an advanced software development toolchain can overcome these challenges. This white paper describes how to generate tight, efficient, and maintainable DSP code for a platform consisting of an IP core based on a specialized instruction-set architecture (ISA) coupled with a DSP-aware toolchain.
Abhishek Bit, CAE, Synopsys; Jamie Campbell, CAE, Synopsys; Sergey Yakushkin, R&D Engineer, Synopsys

Delivering High Quality Analog Video Signals with Optimized Video DACs
In most modern consumer equipment, multimedia content is processed in the digital domain. However, analog video transmission requires the digital video content conversion to the analog domain. To accomplish this, a video digital-to-analog (DAC) must be used. This paper outlines the most common analog video signal standard-specifications that multimedia SoCs must support. It describes the key characteristics and features of a DAC solution optimized for video applications. The paper addresses system-level techniques that together with an optimized video DAC will enable SoC designers to deliver power-efficient and feature-rich multimedia devices.
Antonio Leal, Analog Design Manager, Synopsys



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