Achieving the best performance, power and area (PPA) for processor cores is both a science and an art. A variety of interacting factors affect the achievable performance, power and area for an ASIC design processor implementation. The number of processor cores, the size and organization of cache memories, the underlying silicon process and the range of operating conditions are some of the more common parameters that impact a core's performance, power and area. Other factors, such as standard cells used, test and debug features, power control circuits, clock noise and on-chip variation also play an important role in a CPU and GPU core implementation. Getting from “baseline” results to "expert" results in the fastest possible timeframe often means the difference between product success and failure.
Managing IP integration and the need for processor cores to be tightly integrated and verified with other IP blocks and subsystems on the SoC or chip, is essential. The growing number and complexity of the processor cores and IP blocks and subsystems create challenges for even the most experienced EDA design teams.
Synopsys Professional Services has extensive experience helping designers optimize their cores' results for both CPU and GPU cores. Leveraging leading-edge tools from the Galaxy™ Implementation Platform, optimized core hardening scripts, and the Lynx Design System, Synopsys design consultants help customers meet their processor and chip design goals in the most efficient manner possible while leveraging their expertise in physical design closure and core hardening.
From the earliest phases of physical design feasibility and planning through tape-out, Synopsys Professional Services delivers design flow implementation and verification assistance to design teams while transferring methodology and best practices for the most complex cores from leading vendors such as ARM and Imagination Technologies.
- Key areas of focus in Core Optimization Services include:
- Determining design feasibility and performance estimates
- Core configuration and cache partitioning
- Obtaining an optimal floorplan, including alignment of cache memories
- Addressing test, clock and physical effects early in the synthesis phase
- Managing dynamic and leakage power
- Choosing the best clocking scheme to minimize power and skew
- Timing-optimized placement and critical path optimization
- Ensuring tight correlation between place-and-route and signoff
- Robust DRC closure to avoid late stage surprises
- IP integration and verification
- Deploying core hardening flows/scripts, methodologies and best practices
To get more information on how we can customize our EDA consulting services to meet your project or design goals, please contact Synopsys Professional Services or call your local Synopsys sales representative.