Getting your chips into volume production on a fast, predictable schedule becomes more and more difficult with each new process node. At geometries of 90 nm and below, the risk of a protracted design cycle - and its associated cost burden - becomes a real threat to the health of your business or product development program.
The extraordinary levels of integration afforded by very deep sub-micron (VDSM) processes amplify the challenges in physical design. Closing timing in a predictable manner at both the block and chip levels requires a thorough understanding of VDSM effects. While signal integrity, testability, and power issues are first order considerations, their interdependencies further complicates design closure. Specializing in RTL- to-GDSII design services, Synopsys Professional Services knows that dealing with these and other VDSM factors early in the design flow helps ensure an optimized implementation - without any surprises.
An often-underestimated task that can have a significant impact on design quality and schedule is achieving specification closure, both at the block and chip levels. We work directly with your system architects to ensure the specifications capture design intent, helping to minimize the iterations between the architecture and RTL implementation. In fact, strategic alliances with leading manufacturing service providers enable us to deliver complete Concept-to-Parts solutions, with flexible points for design handoff.
Leveraging Synopsys' technology-leading implementation tools and design flows proven in our own design centers, our consultants help you improve the quality of your design results and get your chips out the door. Our close collaboration with your design team also ensures methodology and knowledge transfer so that you are better prepared for your next round of design challenges.
Implementation Services Highlights
Our services help to complement your design team’s competencies with experienced designed specialists. We help introduce new techniques and methodologies into your design environment for power optimization, core hardening, and IP integration. Through more than 10 years of working with our customers on their most challenging chip designs, Synopsys Professional Services has built a leading-edge design competency and infrastructure, with consultants skilled in the latest EDA technology and design practices. In addition to providing experienced consultants, we can also deploy and customize the Lynx Design System, which combines advanced implementation flows and methodologies into a complete RTL-to-GDSII design environment. We bring that knowledge and expertise to each and every customer engagement, identifying then resolving the design bottlenecks that pose the greatest risks to your project, providing support all the way through tapeout. Whether you need to outsource the entire chip design or augment your team with on-site design assistance - or a combination of the two - Synopsys Professional Services offers flexible engagement models that best address your design goals.
- Our implementation with Galaxy Implementation Platform services include:
- Hierarchical budgeting and design planning
- SI-aware place & route
- Full-chip timing/SI closure, static timing analysis and sign-off
- Qualifying libraries, existing RTL and design constraints
- Generating and optimizing clock trees
- Power planning and optimization
- Full-chip extraction and physical verification
- Support for netlist, placed-gates, or GDSII manufacturing handoffs
- Transferring demonstrated methods and baseline scripts for follow-on project use
- Complete turnkey design solutions with flexible handoffs, from concept to parts
To get more information on how we can customize our services for you, please contact us or call your local sales representative