The quality of early design deliverables such as the chip specification, RTL code and functional verification plan has tremendous impact on the efficiency of an SoC's implementation phase. In addition, the growing number and complexity of IP blocks and subsystems being integrated into today's SoC designs challenge even the most experienced design teams, particularly when the IP is new or otherwise unfamiliar to the team.
Synopsys consultants posses the expertise and experience to assist you in every stage of the SoC design, from the earliest phases of determining design feasibility and performance estimates through IP configuration and integration as well as verification and implementation. Synopsys designers can work directly with your system-level designers to ensure the design specifications accurately capture design intent at both the block and chip levels, helping to minimize iterations between the architecture and RTL implementation to increase productivity. We can then assist your team in translating the specification into a high-quality RTL description following best practices pioneered by Synopsys, as well as help identify and configure suitable IP blocks and subsystems to meet the design goals.
Verification remains the single most significant challenge in getting advanced SoC devices to market. The development of an independent verification plan, separate from the RTL creation, is key to an efficient functional verification approach which will minimize functional bugs. And because traditional verification methods simply cannot scale with chip complexity, our verification experts will help you take advantage of advanced verification techniques such as assertions, constrained-random stimulus generation, and coverage-driven verification, and rapidly deploy them across your project teams. Our consultants share expertise with Synopsys' Discovery™ Verification Platform tools and apply best practices based on the proven methodology defined in the popular Verification Methodology Manual (VMM) for SystemVerilog, co-authored by Synopsys and ARM. Creating a design environment with VMM-compliant building blocks takes less time and eases cross-site collaboration as well as reuse at the block, system and project levels.
By helping you employ the best design practices and the latest design methodologies in the front-end of the design cycle, Synopsys Professional Services enables you to achieve real gains in overall design and verification productivity throughout the entire design process, and improve the predictability of your project schedule.
Synopsys’ IP Integration & SoC Verification services include assistance with:
- Design feasibility, analyzing power, performance, area, complexity, design effort, risks, etc.
- Creation of a functional specification based on design requirements
- Building and configuring complex IP blocks and subsystems for the specific application
- RTL coding and verification
- Developing a robust verification plan including, architecting layered, automated testbenches
- Deploying advanced verification methodologies
To get more information on how we can customize our services for you, please contact us or call your local sales representative.