20nm Solution 

 

The Synopsys Galaxy™ Implementation Platform is being deployed by early adopters of 20 nanometer and smaller geometries. The platform delivers a complete, proven digital and custom implementation solution with multi-foundry-certified physical, timing and signoff tools for 20nm. This solution allows engineers creating Gigascale designs running at Gigahertz+ frequencies designed for Giga-complex processes such as 20nm to achieve predictable and successful design closure.

PDF20nm and Beyond White Paper

 

DC Explorer
Early RTL Exploration Accelerates Synthesis and P&R
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DC Ultra
Best-in-class timing, area and power QoR correlated with physical results
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Design Compiler Graphical
Extends topographical technology to predict & alleviate routing congestion
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Power Compiler
Provides complete solution for power synthesis & optimization PDF
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DFTMAX
Adaptive scan compression for cost-effective DSM testing
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TetraMAX ATPG
Automatic test pattern generation & diagnostics for high-quality tests
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DesignWare IP
Reduce Risk and Speed Time-to-Market with High Quality IP


Formality
Equivalence checking for designs synthesized with DC Ultra
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IC Compiler
IC Compiler Comprehensive Place and Route for established and emerging process
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Custom Designer LE
Custom Layout editor
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Custom Designer SE
Custom Schematic Editor
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Custom Designer SDL
Custom design schematic-driven layout
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PrimeTime
Golden timing sign-off solution and environment
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StarRC
Parasitic extraction
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IC Validator
In-design physical verification solution for 45nm and below
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  • Complete foundry-certified solutions for IC Design, Implementation and Signoff for correct first-time silicon
  • Faster turnaround time with a highly integrated environment for 100M+ instance cell-based and custom designs
  • Predictable, fast closure of Gigahertz+ design performance
  • Comprehensive solution for the new challenges introduced by 20nm manufacturing rules and 3D-IC integration

Design Challenges

The 20nm process node poses significant design and manufacturing challenges that impact the EDA tools.

Complex Double Patterning lithography requirements:
  • Rule-aware placement and routing to ensure ability to color masks correctly and efficiently
  • In-Design physical verification throughout the flow to reduce time-consuming, uncertain iterations
  • Accurate higher levels of extraction and timing analysis to allow for manufacturing variability
Performance and capacity requirements for the next generation designs which require much higher levels of tool interoperability, high degrees of multi-core processing and an integrated design environment to maximize design productivity in particular:
  • Early RTL and design exploration
  • Physical guidance from synthesis to implementation tools
  • Digital and Custom co-design
  • In-Design physical verification with implementation
  • Tightly coupled signoff and implementation tools
  • ECO guidance capabilities
The 20nm process node will enable designs to run at 2GHz+ operating frequency. To achieve this, improved modeling, enhanced guidance and analysis, tools and high degrees of predictability throughout the design flow will be required.
Foundry Partners and Consortiums

Synopsys is actively working with leading 20nm foundries, consortiums and eco-system partners to address the significant challenges with the 20nm process node. This results in availability of foundry certified solutions in the shortest possible time.