Design Challenges
Compared with traditional monolithic ICs, the 3D-IC integration approach of stacking multiple die using through-silicon via (TSV) and silicon interposer technologies is an innovative way to deliver large-scale devices with favorable yield and reliability.
3D-IC technology complements conventional transistor scaling to enable designers to achieve higher levels of integration by allowing multiple die to be stacked vertically, or in a side-by-side "2.5D" configuration on a silicon interposer. 3D-IC integration uses TSV technology, an emerging interconnection technology that will replace the traditional wire-bonding process in chip/wafer stacking, to increase inter-die communication bandwidth, reduce form factor and lower power consumption of stacked multi-die systems.
Synopsys’ 3D-IC initiative begins at the semiconductor device level. Multi-die stacks incorporate different materials, often bonded together, with varying coefficients of thermal expansion (CTE). Any temperature change causes material stress due to thermal mismatch, leading to silicon deformation and affecting transistor performance. Furthermore, TSVs, microbumps and other solder bumps produce a permanent stress in the zone around them. Synopsys’ Sentaurus Interconnect TCAD tool is used to analyze these effects and to model the TSVs in the die stacks, enabling performance and reliability optimization. Semiconductor companies, such as foundries, use the modeling results to create design rules specific to 3D-IC integration to ensure manufacturability and reliability.