3D-IC Design Solutions 

Accelerating 3D-IC Innovation  

3D-IC technology complements conventional transistor scaling to enable designers to achieve higher levels of integration by allowing multiple die to be stacked vertically, or in a side-by-side "2.5D" configuration on a silicon interposer. 3D-IC integration uses through-silicon via (TSV) technology, an emerging interconnection technology that will replace the traditional wire-bonding process in chip/wafer stacking, to increase inter-die communication bandwidth, reduce form factor and lower power consumption of stacked multi-die systems.

 
  • Interconnect Simulation
  • Tools for electrical, stress and reliability analysis of interconnects  

Sentaurus Interconnect
Performs 3D interconnect stress and reliability simulation using design database and process recipes

  • Test Automation
  • Industry's most comprehensive test solutions 

DFTMAX
Adaptive scan compression for cost-effective DSM testing
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  • Memory Test and Repair IP
  • STAR (self-test and repair) Memory System solutions  

DesignWare STAR Memory System
Comprehensive, integrated test, repair and diagnostics solution
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  • Physical Implementation
  • Comprehensive Place and Route System 

IC Compiler II
Netlist to GDSII place and route system enabling 10X faster throughput



IC Compiler
Comprehensive place and route for established and emerging process nodes


  • Custom Implementation
  • Modern-era custom implementation 

Custom Designer SE
Custom Schematic Editor
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Custom Designer LE
Custom Layout editor
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Custom Designer SDL
Custom design schematic-driven layout
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  • Physical Verification
  • Comprehensive physical verification 

IC Validator
In-design physical verification solution for 45nm and below
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  • Signoff
  • Golden, comprehensive signoff solutions 

PrimeRail
In-Design Rail Analysis for Place-and-Route Engineers
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StarRC Ultra
Industry leading parasitic extraction for digital and custom design
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  • Circuit Simulation
  • Performance, accuracy and capacity for AMS verification  

HSPICE
The industry's "gold standard" for accuracy, offers foundry-certified device models with state-of-the-art simulation and analysis algorithms.
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CustomSim
Combines the best-in-class engines of HSIM, NanoSim & XA into a single unified circuit simulation solution
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Key Benefits
  • Synopsys is delivering a comprehensive EDA solution, including enhanced versions of its IC implementation and circuit simulation products, to support 3D-IC design
  • 3D-IC integration technologies offer tangible benefits to boost system performance, reduce form factor and lower power consumption
  • Complements conventional transistor scaling to enable higher levels of integration by allowing multiple die to be stacked vertically, or in a side-by-side “2.5D” configuration on a silicon interposer
  • An innovative way to deliver large-scale devices with favorable yield and reliability

Design Challenges
Compared with traditional monolithic ICs, the 3D-IC integration approach of stacking multiple die using through-silicon via (TSV) and silicon interposer technologies is an innovative way to deliver large-scale devices with favorable yield and reliability.

3D-IC technology complements conventional transistor scaling to enable designers to achieve higher levels of integration by allowing multiple die to be stacked vertically, or in a side-by-side "2.5D" configuration on a silicon interposer. 3D-IC integration uses TSV technology, an emerging interconnection technology that will replace the traditional wire-bonding process in chip/wafer stacking, to increase inter-die communication bandwidth, reduce form factor and lower power consumption of stacked multi-die systems.

Synopsys’ 3D-IC initiative begins at the semiconductor device level. Multi-die stacks incorporate different materials, often bonded together, with varying coefficients of thermal expansion (CTE). Any temperature change causes material stress due to thermal mismatch, leading to silicon deformation and affecting transistor performance. Furthermore, TSVs, microbumps and other solder bumps produce a permanent stress in the zone around them. Synopsys’ Sentaurus Interconnect TCAD tool is used to analyze these effects and to model the TSVs in the die stacks, enabling performance and reliability optimization. Semiconductor companies, such as foundries, use the modeling results to create design rules specific to 3D-IC integration to ensure manufacturability and reliability.