The Synplicity Business Group’s FPGA Design Solution provides designers using FPGAs in their electronic systems with a comprehensive blend of tools, IP, partnerships, methodologies and standards to enable the rapid development and verification of FPGAs.
At the core of the FPGA Design Solution are the Synplify® RTL synthesis products which have set the standard for high quality of results and designer productivity in FPGA implementation. Tight integration with FPGA vendor place and route tools ensures a single source for design constraints throughout the flow boosting designer productivity.
Additional elements of the FPGA Design Solution, which work seamlessly with the synthesis tools, are the Synplify DSP product providing IP and high-level algorithmic synthesis for implementing DSP algorithms in FPGAs; and the System Designer™ tool which assembles IP in the SPIRIT consortium’s IP-XACT format and prepares it for implementation in an FPGA.
ASIC and ASSP designers using a single FPGA prototype to verify their designs also benefit from the Synplicity Business Group’s FPGA Design Solution. RTL and gate-level simulation using Synopsys’ VCS product, combined with the in-system RTL debug technology of the Identify® debugger provide designers with the speed and accuracy required to meet today’s challenging design verification requirements.