|SNUG 2016 Custom Compiler Videolog: Cutting Layout Tasks from Days to Hours |
On March 31, 2016, Synopsys hosted a Custom Compiler Lunch ‘n’ Learn at SNUG Silicon Valley. At this event, attendees heard industry leaders share their experiences using the new Custom Compiler visually-assisted automation to meet the challenges of FinFET custom design, and discuss how it improves their custom design productivity.
AMD, STMicroelectronics, Synopsys IP
|Introducing Custom Compiler Visually-assisted Automation|
Antun Domic, Executive VP and GM of the Design Group unveils Synopsys' next-generation custom design solution.
Custom Compiler brings new levels of productivity to FinFET layout by employing visually-assisted automation technologies that speed up common design tasks, reduce iterations, and enable reuse.
Antun Domic, Executive VP and GM of the Design Group, Synopsys
|IC Compiler II - Accelerating Products to Market with the Power of 10X|
On March 23, 2015, during the 25th annual Synopsys User Group (SNUG) in Silicon Valley, industry leaders shared how 10X faster throughput has transformed the way they think about product development, opening up a world of new opportunities. Watch this video to learn why, just one year after its introduction, IC Compiler II has proven to be a game-changer in physical design.
ARM, MediaTek , Renesas, Synopsys, Toshiba
|Addressing Advanced Design Needs With IC Compiler and IC Compiler II|
On June 2, 2014, Synopsys hosted the 10th annual IC Compiler customer event during the Design Automation Conference (DAC) in San Francisco. Attendees heard industry experts share their experiences using IC Compiler at the latest process nodes. Avago Technologies discussed the deployment of IC Compiler II, Synopsys’ recently introduced place and route solution with the power of 10X, to address their cutting-edge design challenges.
Avago, NVIDIA, Samsung, Synopsys
|Success with the Synopsys Galaxy Implementation Platform|
These highly informative sessions from DAC 2013 cover the latest design trends, challenges and solutions. Hear leading industry experts from LSI, HP and ARM present best practices and their success with Synopsys implementation products. Learn how these customers have accelerated innovation for their Gigascale, GigaHz+, low power and advanced geometry design challenges.
Michael V. Leuzze, Design Center Manager, LSI, Martin Foltin, Master Technologist, HP, Tim Whitfield, Director of Engineering, ARM
|Achieve Gigahertz+ Performance on ARM® Cortex™-A15 Processor |
This videotaped session was jointly delivered by Synopsys and HiSilicon Technologies at ARM TechCon 2012. Synopsys’ Kevin Yip highlighted Synopsys’ high-performance core methodology and key technologies in Design Compiler®, IC Compiler™, PrimeTime® and IC Validator. Featured technologies included physical guidance for implementation predictability, multisource clock tree synthesis for an OCV tolerant clock structure, transparent interface optimization for top-level closure and final stage leakage recovery for leakage power optimization. Chunsheng Liu of HiSilicon Technologies shared HiSilicon’s experience and results on the successful application of these performance and power enabling techniques in the tapeout of a complex ARM Cortex-A15 based SoC design.
Kevin Yip, Senior Applications Consulting (AC) Manager, Synopsys Inc.
Catherine Xiayu, Director of the COT Design Department, HiSilicon Technologies
Chunsheng Liu, Principle Engineer in the COT Design Department, HiSilicon Technologies
|Optimized Implementation of A Gigahertz+ ARM® Cortex™-A15 Processor|
This presentation was delivered by Brian Millar of Samsung at ARM TechCon 2012. Mr. Millar describes how the Synopsys Galaxy™ Implementation Platform was used for a high performance, low power implementation of an ARM® Cortex™-A15 processor for mobile applications. The successful application and trade-offs of key technologies and techniques from synthesis to place and route that enabled high performance were described. Technologies highlighted include topographical synthesis, physical datapath, clock mesh, multivoltage design, and multicorner/multimode optimization, all of which were used successfully by the design team to achieve the aggressive performance/power target and an improvement of 20 percent over traditional implementation techniques.
Brian Millar, Physical Implementation Lead, Samsung Electronics
|High-Performance Physical Design of a 28nm Quad-Core ARM® Cortex™-A15 Processor|
This presentation was delivered by Jason Karka and Michael Robinson of Texas Instruments at Austin SNUG 2012. It highlights key strategies used in a Synopsys IC Compiler™ place-and-route flow for a 28nm quad-core ARM® Cortex™-A15 processor with 4MB L2 Cache. Various physical design techniques were used to obtain very high clock frequencies. Many of these tactics will be of use not only to designers implementing quad-core A15 processors, but also to those designing other 28nm high-performance chips. Topics discussed include net patterning and layer assignment to deal with a tapered metal stack, hierarchical partitioning, placement density and clustering, clock gate cloning, useful skew, logic-level balanced CTS and techniques for post-route setup and hold closure.
Jason Karka, Texas Instruments Designer
Michael Robinson, Texas Instruments Designer
|Trends in Silicon Technologies - Enabling 20nm for Multimedia Convergence |
On June 4, 2012, Synopsys hosted an IC Compiler luncheon during the Design Automation Conference (DAC) where Mr. Philippe Magarshack of STMicroelectronics spoke about enabling 20nm for multimedia convergence.
Philippe Magarshack, Corporate Vice President, Design Enablement & Services, STMicroelectronics
|Designing for GLOBALFOUNDRIES 20nm Technology and Beyond - Winning Through Collaboration|
Dr. Joerg Winkler is a Fellow at GLOBALFOUNDRIES in Dresden, Germany working within the Design Enablement group. On June 4, 2012, Synopsys hosted an IC Compiler luncheon during the Design Automation Conference (DAC) where Dr. Winkler spoke about designing at 20nm technology and beyond.
Dr. Joerg Winkler, Fellow, Design Enablement , GLOBALFOUNDRIES
|GLOBALFOUNDRIES and Synopsys Discuss 20nm enablement|
The 20nm process node poses a number of new, complex design tool challenges. Synopsys’ Andy Biddle asks GLOBALFOUNDRIES’ Richard Trihy how the company plans to enable its customers for this technology.
Richard Trihy, director Design Methodology,
Andy Biddle, product marketing manager, Synopsys
|Design Challenges and Solutions for High-Performance Mobile SoCs |
Samsung Electronics discussed design challenges and solutions for high-performance mobile SoCs during the Synopsys High-Performance Insight Series at DAC 2012.
In this video, Dr. Seomun describes Samsung’s success using the Galaxy™ Implementation Platform on its latest cutting-edge designs.
Jun Seomun, Ph.D. Sr. Engineer, Design Technology Team, Infrastructure Design Center, Samsung Electronics, System LSI
|High-Performance Design on Galaxy Implementation Platform |
During the Synopsys High-Performance Insight Series at DAC 2012, NVIDIA’s Vikas Agrawal discusses NVIDIA’s success designing for high performance using the Galaxy™ Implementation Platform on its latest designs.
VLSI Design Methodology Manager, NVIDIA
|2012 HSPICE SIG Event: Tackling Design Integrity of Multi-Gbps Systems|
On January 31, 2012, Synopsys hosted an HSPICE SIG Event in Santa Clara, CA. At this event, industry leaders spoke about their experiences using HSPICE in some of their most challenging designs.
Tony Todesco, SMTS Design Engineer, AMD; Johann Nittman, Signal Integrity Engineer, Cavium Networks; Liping Li, Sr. Member of the Technical Staff, Altera; Randy Wolff, Manager, Signal Integrity R&D Group, Micron; Scott Wedge, Sr. Staff Engineer, Synopsys
|HSPICE SIG: A Converging Analog World: Silicon, Package and System|
On January 31, 2011, Synopsys hosted its first HSPICE SIG Event in Santa Clara, CA. At this event, industry leaders spoke about using HSPICE in some of today's most challenging designs.
| DAC 2010: Galaxy Implementation Platform Overview|
Steve Smith, Sr. Director of Marketing for the Galaxy Platform provides an overview of the many advancements made in the last year to Synopsys' comprehensive RTL-to-GDSII implementation solution, including a tighter connection between synthesis and place-and-route with physical guidance, new In-Design physical verification, enhanced signoff for large designs, improved multicore capabilities, the Lynx Design System and 28nm readiness.
|IC Compiler In-Design Technology|
At DAC in June 2010, industry experts at AMD, LSI Corporation, Renesas Electronics, Samsung, STMicroelectronics and Texas Instruments presented to over 200 Synopsys guests. The presenters explained how they relied on In-design physical verification with IC Validator for improved productivity and faster design closure.
John Chilton, Moderator, Sr. VP of Marketing & Corporate Development, Synopsys -- Antun Domic, Sr. VP and General Manager of the Implementation Business Unit, Synopsys -- Davide Casalotto, Design Methodologies Project Leader, STMicroelectronics -- Ed Roseboom, Member, Technical Staff, AMD -- Kyle Peavy, Physical Design Engineer, Texas Instruments -- Koki Tsurusaki, Senior Engineer, Back-end Design Technology Development Dept., Platform Integration Division , Renesas Electronics -- Tom Luczejko, Director, Principal Engineer, LSI Corporation -- Harpreet Gill Sr. Engineering Manager, System LSI SoC R&D, Samsung Electronics