|Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform|
This paper explains how the timing ECO flow delivers fast, predictable, signoff-driven timing closure in a single pass. It covers a new physically-aware architecture; which runs on a single machine or across compute farms, on designs with over 100 million instances, and reduces tapeout schedules by weeks during timing closure and signoff; one of the most critical phases of IC design.
James Chuang, Technical Marketing Manager, Synopsys
|FinFET Technology – Understanding and Productizing a New Transistor From TSMC and Synopsys|
This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with
Synopsys, one of their ecosystem partners, to deliver a complete solution. Key elements of this solution include
comprehensive FinFET profiling without impact to design tool runtime and proven, verified IP availability. The
TSMC 16-nm FinFET solution will ensure mutual customers swiftly move to building the next generation SoCs.
Jason S.T. Chen, TSMC; Andy Biddle, Synopsys
|Accelerated Layout for Analog/Mixed-Signal in Nanometer SoCs|
A much more accelerated approach for creating and integrating analog/mixed-signal functions in SoC designs is possible using automated methods to reduce the total effort needed, enable layout to proceed concurrently with circuit design, and typically produce more optimal layouts—especially for smaller die sizes.
Lyndon Lim, Synopsys
|IC Compiler : Multi-Source CTS|
Multi-Source CTS delivers the ideal hybrid solution for designers seeking the best of conventional CTS and pure clock mesh. IC Compiler Multi-Source CTS provides better high-speed performance and OCV tolerance than conventional CTS and is more tolerant of complex floorplans and provides more flexibility for clock gating depth than pure clock mesh.
Harvey Toyama, Synopsys Implementation Group
|Accelerating Analog Simulation with HSPICE Precision Parallel Technology|
HSPICE Precision Parallel technology is a new multicore transient simulation extension to HSPICE for both pre- and post-layout of complex analog circuits such as PLLs, ADCs, DACs, SERDES, and other full mixed-signal circuits. HPP addresses the traditional bottleneck in accelerating SPICE on multicore CPUs with new algorithms that enable a larger percentage of the simulation to be parallelized, with no compromise in golden HSPICE accuracy. Additionally, efficient memory management allows simulation of
post-layout circuits larger than 10 million elements.
Robert Daniels, Sr. Staff Engineer, Synopsys Inc.; Harald Von Sosen, Principal Engineer, Synopsys Inc.; Hany Elhak, Product Marketing Manager, Synopsys Inc.
|Improve Design Productivity with Quality Checks on IP Timing Constraints|
When combining intellectual property (IP) blocks from various sources, the chip-level implementation teams may not have the detailed IP knowledge required to develop timing constraints for the IP.
|Design Compiler Technology Backgrounder|
Synopsys’ RTL synthesis solution has been the No. 1 choice of ASIC designers worldwide since 1987.
Countless numbers of chips have been designed using Synopsys’ synthesis solution and over 60
semiconductor and library vendors offer hundreds of libraries supporting Synopsys synthesis.