The Galaxy™ Design Platform is a comprehensive solution for cell-based and custom IC implementation. Galaxy accepts design intent in industry standard formats and generates a production ready IC design in GDSII format. Galaxy RTL
and Physical implementation
products concurrently balance design constraints by performing intelligent tradeoffs between speed, area, power, test and yield. Galaxy Signoff
engines accurately model complex physical interactions to ensure signal and power integrity. Coherent algorithms for parasitic extraction and timing produce correlated results.
The Galaxy™ Design Platform provides a comprehensive suite of tools that are being deployed worldwide targeting established process node designs as well as emerging process node FinFET designs at 20nm and below.