Low Power Verification 

Comprehensive Solution for Low Power Design Verification 

Low Power Verification

The Synopsys advanced low power solution provides comprehensive power-aware functional and static verification for all phases of the advanced low power design flow. Architectural and structural MV checking enable validation of power intent at RTL, netlist, and PG netlist stages. True voltage-aware power network simulation allows verification of advanced low power designs employing multiple voltage supplies, power shutdown, and dynamically varied voltage levels.

With over 15 years of proven low power innovations, Synopsys continues to provide the most complete solution for addressing the latest in low power design challenges.


Key issues for chip developers are designing for low power and energy consumption optimization

The most comprehensive and accurate low power verification and debug solution

Functional verification for full custom designs

Comprehensive, fast, intuitive equivalence checking

The industry's most comprehensive portfolio of analog and mixed-signal simulation and optimization solutions

Key Benefits
  • Comprehensive power-aware functional and static verification enable validation of advanced LP designs from RTL to signoff
  • Automated, production-proven multi-voltage flow reduces risk of escaped failures
  • True voltage-aware power network simulation enables accurate validation of multiple and dynamically varying voltage levels
  • Architectural and structural MV low power checking at RTL, netlist, and signoff phases
  • Automated and user-controlled MV assertions reduces development effort, ensures complete coverage of power behavior
  • Consistent interpretation of power intent across the tool flow minimizes manual intervention

Verification of today’s SoC designs is one of the industry’s biggest challenges. The explosion in complexity requires that verification and coverage issues be considered from the early architectural phase all the way through design tapeout.

Advanced low power design techniques add another dimension to the verification problem by introducing power-off conditions and variable voltages into the mix, requiring complete validation under all conditions and modes of operation. The resulting problem can only be addressed through the use of power-aware tools throughout the verification flow, with a combination of static and dynamic verification techniques to achieve high verification coverage of the functional aspects as well as the low power features in the design.

The Discovery Verification Platform includes complete low power verification capabilities to ensure correctness and completeness of designs, fully integrated to minimize verification time and design risk.