Discovery Low Power Verification

Comprehensive Solution for Low Power Design Verification

The Synopsys advanced low power solution, featuring the Discovery Verification Platform, provides comprehensive power-aware functional and static verification for all phases of the advanced low power design flow. Architectural and structural MV checking enable validation of power intent at RTL, netlist, and PG netlist stages. True voltage-aware power network simulation allows verification of advanced low power designs employing multiple voltage supplies, power shutdown, and dynamically varied voltage levels.

With over 15 years of proven low power innovations, Synopsys continues to provide the most complete solution for addressing the latest in low power design challenges.

Tools
Benefits
Challenges
Resources

System-Level Low Power
Early consideration of power consumption maximizes impact. more

Key issues for chip developers are designing for low power and energy consumption optimization

Low Power Verification
Identify power management bugs to reduce or eliminate respins more

	MVRC	Sign-off quality low power static checking in UPF-based RTL-to-Gates implementation flows

	VCS with MVSIM Native Low Power (VCS NLP)	The most comprehensive and accurate voltage-aware simulation

Formal Equivalence Checking
Comprehensive, fast, intuitive equivalence checking more

	ESP-CV	Functional verification for full custom designs

	Formality	Comprehensive, fast, intuitive equivalence checking DOWNLOAD DATASHEET (PDF)

AMS Verification
Analog/mixed-signal verification more

The industry's most comprehensive portfolio of analog and mixed-signal simulation and optimization solutions

Key Benefits

Challenges
Verification of today’s SoC designs is one of the industry’s biggest challenges. The explosion in complexity requires that verification and coverage issues be considered from the early architectural phase all the way through design tapeout.

Advanced low power design techniques add another dimension to the verification problem by introducing power-off conditions and variable voltages into the mix, requiring complete validation under all conditions and modes of operation. The resulting problem can only be addressed through the use of power-aware tools throughout the verification flow, with a combination of static and dynamic verification techniques to achieve high verification coverage of the functional aspects as well as the low power features in the design.

The Discovery Verification Platform includes complete low power verification capabilities to ensure correctness and completeness of designs, fully integrated to minimize verification time and design risk.