Articles 


Power Reduction Techniques
Are they all the same for established planar, FD-SOI and finFET transistors?
Aug 07, 2014

FinFET variability issues challenge advantages of new process
Tool and process vendors are having to work hard to ensure that designers can overcome finFET variability issues to extract the full benefits of the new processes, according to speakers at a recent SNUG meeting in Santa Clara.
Apr 16, 2014

What Makes FinFETs So Compelling?
Oct 08, 2013

FinFET race holds promises, perils
Targeting chips in late 2014
May 27, 2013

Physical verification of FinFET and FD-SOI devices
A look at some of the design and physical verification challenges of working with FinFET and FD-SOI devices, including their impact on layout, DRC and LVS.
May 02, 2013

Analysis of TSV proximity effects in planar MOSFETs and FinFETs
The impact of TSV-induced stresses on transistor performance are simulated, and a "keep-out-zone" is identified
May 01, 2013

The Use of FinFETs in IP Design
Recent announcements of FinFET roadmaps accelerated the discussion about the opportunities and challenges associated with the use of FinFETs in IP design.
Apr 23, 2013

DATE: Early shift to finFET processes challenges IP development strategies
An early shift to finFET-based processes (Guide) is making the process of developing supporting IP libraries more challenging.
Mar 20, 2013

Manhattan And Mr. Spock Offer Lessons In 3D FinFET Design
Also known as 3D transistors, FinFETs provide a significant speed boost while cutting dynamic power in half and static power by as much as 90%. They're also the next big thing in low-power computing. 
Jan 15, 2013

FinFETs Herald A Seismic Shift In Semiconductor Technology
When making the transition from planar devices to FinFETs, IP design challenges arise that require education and experience when dealing with the complexities
Jan 15, 2013

Combining Tools and Technology for 20nm Gigascale ICs
Synopsys and Samsung explain how they are aligning their respective technology roadmaps to address the emerging challenges for next-generation 20nm process nodes.
May 01, 2012




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