Are Standard Cell Libs, Memories and Mixed-signal IP Available at 7nm FF? - SemiWiki
May 05, 2016

FinFET Design Enablement - SemiWiki
EDA companies, IP providers and foundries have... closely collaborated to enable the FinFET revolution that we are now witnessing in production quantities for 2015.
Mar 10, 2015

FinFETs Race Toward Silicon - EETimes
Galaxy Design Platform has been used by 90 percent of the production-bound FinFET chips that have taped out to date.
Mar 10, 2015

Synopsys Claims FinFET Leadership - Tech Design Forum
All the foundries offering FinFET processes have used and qualified the Galaxy Design Platform, including GlobalFoundries, Intel Custom Foundry, Samsung and others.
Mar 10, 2015

Is FinFET Process the Right Choice for Your Next SoC? – DesignWare Technical Bulletin
Learn about the benefits and challenges of moving from a planar CMOS process to FinFET and how DesignWare embedded memory and logic library IP can enable this move.
Jan 20, 2015

Synopsys addresses FinFET defects, embedded-flash test at ITC - EE Evaluation Engineering
Learn about the defect-detection enhancements in TetraMAX ATPG through slack-based cell-aware test capability, and about the new STAR (self-test and repair) Memory System for embedded flash.
Oct 23, 2014

Six key criteria for deciding to migrate to a finFET process – Tech Design Forum
Learn about the benefits and challenges of moving from a planar CMOS process to FinFET and how DesignWare embedded memory and logic library IP can enable this move.
Aug 27, 2014

FinFETs for your Next SoC –
Should your next SoC design use a FinFET process? It all depends on what your product requirements are, and which libraries are available to implement your design.
Aug 24, 2014

USB 3.0 IP on FinFET may stop port pinching –
Learn how Synopsys USB 3.0 femtoPHY IP may finally remove the urge to port pinch in SoC designs and help expand USB 3.0 adoption more quickly.
Aug 19, 2014

Power Reduction Techniques
Are they all the same for established planar, FD-SOI and finFET transistors?
Aug 07, 2014

Designing for Success: USB IP for FinFET Processes – DesignWare Technical Bulletin
Learn about the challenges associated with FinFETs, including the process complexities in modeling, parasitic extraction, power swings, fin width considerations and even lithography and manufacturing.
Jul 22, 2014

FinFET variability issues challenge advantages of new process
Tool and process vendors are having to work hard to ensure that designers can overcome finFET variability issues to extract the full benefits of the new processes, according to speakers at a recent SNUG meeting in Santa Clara.
Apr 16, 2014

What Makes FinFETs So Compelling?
Oct 08, 2013

FinFET race holds promises, perils
Targeting chips in late 2014
May 27, 2013

Physical verification of FinFET and FD-SOI devices
A look at some of the design and physical verification challenges of working with FinFET and FD-SOI devices, including their impact on layout, DRC and LVS.
May 02, 2013

Analysis of TSV proximity effects in planar MOSFETs and FinFETs
The impact of TSV-induced stresses on transistor performance are simulated, and a "keep-out-zone" is identified
May 01, 2013

The Use of FinFETs in IP Design
Recent announcements of FinFET roadmaps accelerated the discussion about the opportunities and challenges associated with the use of FinFETs in IP design.
Apr 23, 2013

DATE: Early shift to finFET processes challenges IP development strategies
An early shift to finFET-based processes (Guide) is making the process of developing supporting IP libraries more challenging.
Mar 20, 2013

FinFET Design, Manufacturability, and Reliability – DesignWare Technical Bulletin
In this article we will discuss the design opportunities and challenges of the FinFET device and link them to the manufacturing and reliability challenges associated with further scaling.
Jan 22, 2013

Manhattan And Mr. Spock Offer Lessons In 3D FinFET Design
Also known as 3D transistors, FinFETs provide a significant speed boost while cutting dynamic power in half and static power by as much as 90%. They're also the next big thing in low-power computing. 
Jan 15, 2013

FinFETs Herald A Seismic Shift In Semiconductor Technology
When making the transition from planar devices to FinFETs, IP design challenges arise that require education and experience when dealing with the complexities
Jan 15, 2013

Combining Tools and Technology for 20nm Gigascale ICs
Synopsys and Samsung explain how they are aligning their respective technology roadmaps to address the emerging challenges for next-generation 20nm process nodes.
May 01, 2012

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