Webinars 

Counting Down to 10 nm: GLOBALFOUNDRIES and Synopsys Perspective on Future Extraction
GLOBALFOUNDRIES and Synopsys will discuss the implications for extraction as foundries move to the next level of die shrink at 10nm.
Jongwook Kye, Fellow, GLOBALFOUNDRIES; Beifang Qiu, Senior R&D Manager, Synopsys
Apr 30, 2014
 
Advanced Design with Smart Power BCD Technologies
Join STMicroelectronics and Synopsys as they discuss the applications of existing and upcoming smart power BCD technologies, along with design and verification solutions to help you achieve results.
Pier Luigi Rolandi, Sr. Director, Design Enablement, Technology R&D Smart Power, STMicroelectronics; Marco Casale-Rossi, Product Marketing Manager, Implementation Group, Synopsys
Feb 20, 2014
 
TSMC and Synopsys at 16nm: Collaborating to Create Comprehensive Solutions for Optimal FinFET Design
TSMC and Synopsys describe their broad, co-developed solutions for 16-nm design that are architected to bring the fastest node enablement to their mutual customers.
Chiming Li, Technical Manager Design Methodology & Service Marketing Program, TSMC; Dr. Henry Sheng, Senior Director of R&D, Synopsys
Nov 05, 2013
 
Samsung Foundry and Synopsys Discuss Enabling 14-nm FinFET Design
Samsung Foundry and Synopsys present the challenges and opportunities of manufacturing with Samsung's 14-nm FinFET process and how these changes impact design enablement.
Dr. Kuang-Kuo Lin, Director, Foundry Design Enablement, Samsung Semiconductor Inc. (SSI); Dr. Henry Sheng, Senior Director of R&D, Synopsys
May 28, 2013
 
Designing with FinFETs
Learn about the benefits and challenges of transitioning from planar to FinFET technologies and their implications for IP design.
Jamil Kawa, Group Director, Solutions Group, Synopsys
Mar 14, 2013
 
Double Patterning Ready Extraction and Signoff: TSMC and Synopsys Update
Learn how double patterning technology (DPT) has emerged as a critical technique to ensure printability of device and interconnects layers in IC manufacturing.
Anderson Chiu, Technical Manager, TSMC; Beifang Qiu, Senior R&D Manager, Synopsys
Dec 05, 2012
 
Double Patterning Ready Extraction and Signoff: TSMC - Simplified Mandarin
Learn how double patterning technology (DPT) has emerged as a critical technique to ensure printability of device and interconnects layers in IC manufacturing.
Anderson Chiu, Techincal Manager, TSMC; Beifang Qiu, Senior R&D Manager, Synopsys
Dec 05, 2012
 
Double Patterning Ready Extraction and Signoff: TSMC and Synopsys Update - Traditional Mandarin
Learn how double patterning technology (DPT) has emerged as a critical technique to ensure printability of device and interconnects layers in IC manufacturing.
Beifang Qiu, Technical Manager, Synopsys; Anderson Chiu, Senior R&D Manager, TSMC
Dec 05, 2012
 
FinFET Process Modeling and Extraction at 16-nm and Below
Synopsys' R&D will discuss the motivation behind FinFETs and describe how Synopsys is driving the collaboration with major foundries to develop a next-generation extraction solution.
Bari Biswas, Senior Director R&D, Synopsys
Sep 27, 2012
 


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