Technical Papers 

2013 SNUG Silicon Valley
Using the Lynx Design System to Lower the Cost of Bringing up a New Flow on a New Node
In this paper, we will take you through the process of migrating to full Synopsys-based RTL-to-GDSII flow from the prospective of a company focused on controlling design costs, evalu-ating different process technologies, quickly integrating third-party IP, getting to a stable flow deployed to the design team as quickly as possible, and maximizing the performance of the design.
Simone Borri, Pierre-Marie Signe, Christian Eichrodt, Abilis Systems; Riccardo Giordani, Synopsys GmbH

Standardized design environment and methodologies enable simultaneous implementation of 28nm designs with a single flow
Using a configurable, pre-validated standardized flow and integrated GUIs in Synopsys' Lynx Design System, we were able to quickly deploy a new 28-nm RTL-to-GDSII flow. This environment allows our geographically distributed engineers to simultaneously work on multiple projects targeting different technologies.
Cyrille Thomas, BULL

2013 SNUG France
Concurrent Top and Blocks Level Implementation of a High Performance Graphics Core Using One-Pass Timing Closure in Synopsys IC Compiler
Implementing a High Performance Graphics Core with complex low-power features and several operating points in an advanced design node (28nm FDSOI) challenges the traditional Place and Route flow. Adding a very short schedule and improving the resource utilization for the execution of this multi-millions instances design through a Hierarchical Physical Implementation is asking for an innovative one pass timing closure flow. This article will describe how, using IC Compiler (ICC) through a top-down approach and concurrent top and blocks implementation methodology, the target frequency, the power constraints and the schedule can be achieved successfully. From the Design Planning stage to the Signoff, we will tackle the following aspects in ICC: usage of Black-Boxes for early Design Planning, Budgeting and advanced Placement and Optimization, targeting PrimeTime SI Signoff for final ECO, with specific considerations on the SDC blocks budgets and QTM models handling.
Corine Pulvermuller & Julien Guillemain, STMicroelectronics



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