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Addressing the Complexity of "Smart" Devices Through Low Power Hierarchical Design
This paper will describe methodologies and flow automation for creating successful low power hierarchical designs. Specifically, this paper will demonstrate the use of UPF-based methodologies to implement and analyze a low power hierarchical design with bottom-up and top-down flows. The content draws on features of Synopsys' Galaxy™ Implementation Platform tools and the Lynx Design System, as well as the experience of design consultants in Synopsys Professional Services who have applied these techniques to multiple leading edge SoC design projects.
Chad Gamble, CAE; Terry O'Brien, R&D; Synopsys, Inc.

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