System-to-Silicon Verification Solution 

Accelerate Your Innovations with the Most Comprehensive Verification Solution 

The System-to-Silicon (S2S) Verification Solution delivers powerful capabilities to solve increasingly difficult challenges across numerous verification domains and provides critical links to higher levels of verification at all levels in the process. This winning mix of technology, models, integrators, best practices and ecosystem enables you to be more productive and bring compelling products to market more rapidly than ever before.

 

We are witnessing the emergence of designs with unprecedented complexity, size and software content. Couple this with multiple cores, increasing analog content, multiple bus interface standards, growing algorithmic content and interaction with complex physical systems and you have verification costs (in scope, schedule, and resources) like never before.

To address this daunting problem, multiple verification challenges across several design domains — from system-to-silicon (S2S) — must be considered together. Examples include incorporating embedded software data in the RTL testbench, providing a test and debug environment to the embedded software teams, determining that the implemented design is true to the original specification, determining the right amount of analog/digital simulation and reaching coverage goals in as little time as possible.

To get from an optimal specification to a fully verified system, while addressing the full range of verification challenges — on schedule and within budget —five solution elements are needed:

Technology: tools with high performance, capacity and debug capabilities for all verification domains
Models: proven, pre-verified IP at all verification levels and design domains
Integrators: tool interfaces for verification and debug across all domains
Best Practices: structured verification methodology, services, training and technical resources
Ecosystem: 3rd party alliances and standards for interoperability

The Synopsys S2S Verification Solution includes our top performing verification tools to provide the industry’s most complete multi-level verification environment. Here, we’ll provide some details in the context of the aforementioned solution elements and we’ll share some examples of Synopsys customers tackling the world’s most pressing verification problems.

Solving the multitude of S2S verification challenges (see examples in Overview tab) requires high performance, high capacity tools with rich capabilities to address the simulation, validation and debug challenges across multiple design abstractions (e.g. system-level design (ESL), functional design (RTL), analog/mixed-signal (AMS), HW/SW and physical systems).

Listed below are brief descriptions of the Synopsys S2S Verification Solution tool technologies within the respective verification domains.

System & Software Verification
Algorithm development and validation with SPW and System Studio
Create optimal algorithms in less time and use them as fast reference models in VCS functional simulation testbenches

Platform Architect
Perform fast simulation and performance analysis for the optimization of multi-core SoC architectures with SystemC TLM tools and methods

Synphony C Compiler and Synphony Model Compiler
Specify designs at a very high level of abstraction using C/C++ languages or IP model libraries, and generate optimized RTL and testbenches for ASIC and FPGA, FPGA-based and Virtual Prototyping, and for verification using C or RTL

Processor Designer
Achieve the full potential (optimize trade-offs between flexibility, reuse, power, performance, area) of application specific processors (custom processors) with this single input solution and dramatically accelerate design, verification and software development

Virtual Prototyping
Virtual prototypes are fast, fully functional software models that execute unmodified production code and provide a higher debugging/analysis efficiency. They enable software-driven verification, embedded software development, integration and test, and supply chain enablement. Virtual prototyping results in faster time-to-market through both earlier (pre-RTL) and faster development.

FPGA-Based Prototyping with HAPS
Enable early software development and accelerate functional verification of ASIC, ASSP, and SoC designs with a complete hardware plus software solution, including integrated co-simulation, transaction-based verification and links to virtual prototyping capabilities.

Power Electronics Systems / Mechatronic Systems simulation with Saber
Optimize the physical system for reliability, performance and cost without the need for hardware prototypes

Functional Verification
RTL verification and debug with VCS, Magellan, MVSIM and more
Complete RTL simulation with the industry’s highest performing, highest capacity and most comprehensive verification technologies, SystemVerilog support and unified debug environment

Analog/Mixed-Signal (AMS) Verification
FastSPICE simulation with CustomSim
CustomSim delivers superior transistor-level verification performance and capacity for all classes of designs including custom, digital, memory, and analog/mixed-signal.

A solid foundation of tool technologies must be complemented by proven models and IP at all levels throughout the S2S Verification flow. Synopsys delivers the industry leading libraries, models, and pre-verified IP at each level.

Listed below are brief descriptions of the Synopsys S2S Verification Solution models and IP within the respective verification domains.

Models for System Verification
Algorithm Development
System Studio Libraries – 3,000+ modifiable DSP simulation models. Model categories include Sources, Basic Operations, Encoder/Decoder, Modulation/Demodulation, Filter, Channels, Equalizer, Sinks, Logic, Flow Control and Conversion

SPW Model Libraries – Physical layer baseband simulation models of wireless standards. DSP Model Libraries available include the Communications Library, LTE Library, LTE Library for Xilinx IP, WCDMA (3GPP) Library, TD-SCDMA Library, GSM/GPRS/EDGE Library, WiMAX Library, CDMA2000 (3GPP2) Library and WLAN/WPAN Library

Architecture Design
Architecture Design Models – SystemC TLM models for SoC architecture exploration and validation. Highlights include models from leading IP providers including ARM, MIPS and Tensilica such as Traffic Generators, Interconnect models, Memory Subsystem models and Processor models

Virtual Prototyping
DesignWare TLM Library – SystemC Models representing DesignWare Interface IP including USB, AMBA, SATA, Ethernet, GMAC, PCIe, and HDMI

System-Level Libraries – Comprehensive set of transaction level models (TLM) including Embedded Processor models, Peripheral models and Custom Processor models developed in partnership with major IP providers, including market leaders ARM, IBM, MIPS, Tensilica, and CEVA

CoMET/METeor Models – Fast and accurate virtual processor models (VPM) for Automotive and Consumer IP developed in partnership with leading semiconductor suppliers including Freescale, Renesas, Infineon, Toshiba and CEVA

Pre-assembled Prototypes – Reference virtual prototypes of processors from TI, Freescale, Marvell and ARM

Physical Systems (power electronics / mechatronic) Simulation
Saber Component and Templates Libraries – 30,000+ characterized device models and model templates across multiple engineering domains such as electrical/electronic, mechanical, thermal, hydraulic, and magnetic. Power electronic model highlights include components such as BJTs, MOSFETS, IGBTs, Diodes, and PWMs from a host of major vendors such as TI, IRF, Fairchild, Philips, Toshiba, Mitsubishi, and Motorola

FPGA-based Prototyping
DesignWare IP – Synthesizable IP cores, bus interfaces and more extend the value of FPGA prototypes. Examples of DesignWare’s industry leading IP portfolio include Interface IP, Analog IP, Embedded Memories, Logic Libraries, SoC Infrastructure, as well as Configurable Cores from providers such as ARM and Synopsys.

Models for Functional Verification
HDL Simulation
Synopsys Verification IP – Broad Verification IP (VIP) portfolio of the most popular bus interface protocols including USB 3.0, AMBA, SATA 6G, Ethernet, PCIe, HDMI, MIPI and more.

Models for Analog/Mixed-Signal (AMS) Verification
HSPICE IDM and Foundry Certified Models – HSPICE supports all industry standard analog simulation models, such as BSIM, PSP and HiSIM. Synopsys also develops HSPICE models for specific applications, such as HVMOS and TFT. With the HSPICE Common Model Interface (CMI), users can develop their own models that may then be used with HSPICE, HSPICE RF and CustomSim (FastSPICE).

A comprehensive selection of technology (tools) and models must include the simulation interfaces and standards support enabling verification and debug across all verification domains. Following is a description of these critical links within the context of the verification domains and the technologies they connect.

Integrators for System, Software and Functional Verification
Subsystem models created in System Studio, SPW, Synphony, Processor Designer, Saber and 3rd party tools can be reused inside Synopsys Virtual Prototyping tools to enable software verification through C or SystemC TLM (Transaction Level Model) interfaces. Individually, or as part of a Virtual Prototype, these subsystem models can be used in VCS for speeding testbench creation or providing reference models for use in scoreboard comparison. To enable these capabilities, a variety of interfaces (PLI, SystemC) are supported to connect with VCS for hardware verification, and still others (SCI-ME, UMRBus - Universal Multi-Resource Bus) to integrate the HAPS FPGA-based Prototyping solution with VCS and Virtual Prototypes.

Integrators for Functional and AMS (Analog Mixed-signal) Verification
For comprehensive mixed-signal verification, the CustomSim solution is tightly integrated through a direct kernel interface with the VCS functional verification solution for multi-language support, including SystemVerilog, Verilog, VHDL and Verilog-AMS.

A winning verification strategy must include structured methodology support and access to professional services and technical resources. The following best practices provide this framework for maximizing verification success.

Structured Methodology support
  • VMM (Verification Methodology Manual)
  • Provides proven industry best practices for the creation of robust, reusable, and scalable verification environments using the SystemVerilog language standard
    • VMM for System Verilog
    • VMM for Low Power
  • UVM (Universal Verification Methodology)
    Accellera standard for universal VIP (Verification IP) interoperability
  • OVM (Open Verification Methodology)
  • FPMM ((FPGA-based Prototyping Methodology Manual)

Services

Training

Web resources

A project supportive environment composed of partnerships, interoperability, standards and services is a valued and growing attribute of the Synopsys S2S Verification Solution.

3rd Party Solutions & Partners
Standards
  • SystemVerilog
  • Verilog
  • VHDL
  • SystemC
  • OpenVera
  • C/C++
  • OpenMAST
  • VHDL-AMS
  • Verilog-AMS
  • SCI-MI
  • VMM
  • UPF
  • UVM