Platform Architect   

SoC Architecture Performance Analysis and Optimization 

While spreadsheets are good for aggregating data, static spreadsheet calculations are not accurate enough to estimate performance and make design decisions. Simulation is needed. Traditional RTL simulation is too slow and lacks the configurability and visibility to analyze performance. In addition, the RTL may simply not be available. Risks include over-design, under-design, cost increases, schedule delays and re-spins.

Synopsys Platform Architect with Multicore Optimization Technology provides architects and system designers with SystemC TLM tools and methods for the efficient design, performance analysis and optimization of multicore SoC architectures. To accelerate architecture design, also take advantage of the Architecture Design Models, and CoStart Enablement Services.
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Highlights
  • Hardware-Software Partitioning and Optimization of Multicore Systems
  • SoC Interconnect and Memory Subsystem Performance Optimization
  • Efficient Exploration Using Traffic Generation & Cycle-Accurate TLM Interconnect Models
  • Powerful Performance Analysis Visualization for Root-Cause Analysis
  • Spreadsheet-In/Spreadsheet-Out Sensitivity Analysis
  • Hardware-Software Validation Using Cycle-Accurate TLM Processor Models
  • IEEE 1666-2011 SystemC TLM-2.0 Standards-based Environment

Synopsys Platform Architect is a SystemC TLM standards-based graphical environment for capturing, configuring, simulating, and analyzing the system-level performance of multicore systems and next-generation SoC architectures. Platform Architect enables system designers to explore and optimize the hardware-software partitioning and the configuration of the SoC infrastructure, specifically the global interconnect and memory subsystem, to achieve the right system performance and cost.

Its efficient turnaround time, powerful analysis views, and available models make Platform Architect the premier choice for system-level performance analysis and optimization of ARM AMBA-based SoCs. Platform Architect is a production-proven solution for embedded systems architecture used by leading systems OEMs and semiconductor companies worldwide.

Hardware-Software Partitioning and Optimization of Multicore Systems
Platform Architect with Multicore Optimization Technology enables architects to create task-driven workload models of their end-product application for early architecture analysis.
  • Generic task models are easily configured to create a SystemC performance model of the application, called a task-graph
  • Using the task-graph, the performance workload of parallel application tasks are mapped onto Virtual Processing Unit (VPU) task-driven traffic generators
  • Simulation and task analysis enables hardware-software partitioning to be optimized for best system performance well before the application software is available
  • Task graphs are fully reusable as task-driven traffic generators for Interconnect and Memory Subsystem Performance Optimization in combination trace-driven traffic generation
Interconnect and Memory Subsystem Performance Optimization Using Trace-Driven Traffic Generation
Trace-driven traffic generation enables architects to focus on the challenges associated with the optimization and performance validation of the backbone SoC interconnect and global memory subsystem.
  • Dynamic application workloads are modeled using traffic generation, enabling early measurement of system performance before software is available
  • Simulation sweeping enables performance data to be collected parametrically, exploring all traffic scenarios against the complete of range architecture configurations
  • Powerful tools for analysis visualization provide graphical transaction tracing and statistical analysis views that enable you to identify performance bottlenecks, determine their root-cause and examine the sensitivity that system performance may have to individual or combined parameter settings
  • The result is an executable specification used to carefully dimension the SoC interconnect and memory subsystem to support the latency and bandwidth requirements of all SoC components, under all operating conditions
Hardware-Software Performance Validation Using Processors Models and Critical Software
After exploration the performance model of the candidate architecture can be refined to replace the trace-driven and task-driven traffic generators with cycle-accurate processor models.
  • This enables architects to validate the candidate architecture using the available performance critical software
  • Software and hardware analysis views can be visualized together to provide unique system-level visibility to measure performance and confirm goals are met
Complete IEEE 1666-2011SystemC TLM-2.0 Standards-based Environment
Synopsys Platform Architect is a native SystemC environment fully compatible with the IEEE 1666-2011 SystemC TLM-2.0 Language Reference Manual (LRM). It supports the assembly, simulation and analysis of models containing mixed levels of abstraction including:

  • SystemC transaction-level models using IEEE 1666-2011 TLM-2.0 and Accellera Systems Initiative (ASI) TLM industry standards, and the open Synopsys SystemC Modeling Library (SCML) API library for highly reusable TLM-2.0 based peripheral modeling

  • Mixed SystemC / HDL co-simulation with Synopsys VCS and other third party HDL simulation environments enabling reuse of RTL memory controllers and other IP components

  • Plus, models used in Platform Architect for performance analysis can be reused to accelerate the creation of virtual platforms with Synopsys Virtual Prototypes for software development and software-driven verification