Signal processing designers today need high-level synthesis optimization technologies that deliver high quality of results for FPGA and ASIC while enabling rapid exploration of performance, throughput, power, and area tradeoffs. Synphony High-Level Synthesis (HLS) tools provide an efficient path from algorithm concept to silicon and enable greater design, C model and testbench generation to accelerate simulation productivity. Synphony C Compiler
and Synphony Model Compiler
provide an optimized implementation path from C/C++ and high-level fixed-point models into RTL. With Synphony, users can specify designs at a very high level of abstraction using C/C++ languages or IP model libraries, and then use the Synphony HLS compilers to create optimized RTL and testbenches for ASIC and FPGA, FPGA-based
and virtual prototyping
, and for verification using C or RTL.