FPGA-Based Prototyping  

Scalable Prototyping System Accelerates Hardware and Software Development 

Many design and validation teams are increasingly using FPGA-based prototyping to meet time-to-market windows. Synopsys’ FPGA-based Prototyping Solution improves time-to-market and helps avoid costly device re-spins by enabling early embedded software development and allowing hardware and software co-design well ahead of chip fabrication. Together, our suite of tightly integrated and easy-to-use HAPS hardware plus software tools dramatically accelerate software development, hardware/software integration and system validation from individual IP blocks to processor subsystems to complete SoCs.

HAPS systems are also supported by an ecosystem of third-party vendors from the Synopsys HAPS Connect Program that provide daughter boards, services and hardware for HAPS.

 
  • HAPS
  • FPGA-Based ASIC Prototyping Solutionmore

HAPS-DX
Uses Xilinx Virtex®-7 FPGAs for capacity up to 4 million ASIC gates
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HAPS-70
Uses Xilinx Virtex®-7 FPGAs for capacity up to 144 million ASIC gates
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ProtoCompiler
Design Automation and Debug for the HAPS Series
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Partition SoC design blocks between Virtualizer™ virtual prototyping and HAPS FPGA-based prototyping environments for best overall prototype performance and availability.
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The Certify multi-FPGA implementation and partitioning tool combines RTL multi-chip partitioning with best-in-class FPGA synthesis.
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Synplify Premier software enables easy conversion of ASIC-style designs and implementation into the HAPS prototyping system.
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Synopsys FPGA-Based Prototyping Solution Brings It All Together
The Synopsys FPGA-based prototyping solution is a complete hardware-assisted system validation environment based on our HAPS® High-performance ASIC Prototyping System ™ supported by a comprehensive design automation and debug environment called ProtoCompiler.

Benefits of the Synopsys FPGA-based prototyping solution include:
  • 3-6 month shorter design schedules by enabling earlier embedded software development
  • Eliminate redundant IP prototyping tasks by using pre-tested DesignWare IP components
  • Maximize ROI by applying the modular system across multiple projects
  • Lower risk with a proven solution used by more than 300 customers
  • Improve product quality with a high-performance system that will support real-world interface testing
  • Portable and cost effective to deploy prototypes to software development teams
  • Freely combine RTL and other model formats like SystemC to create hybrid prototypes for even earlier availability
  • Immediate product availability using the latest generation of FPGA device families bypasses bring-up effort and expense of custom-built systems
  • Reliable for maximum up-time with sophisticated PCB technology and advanced power and heat management
  • Easy deployment and sharing via a network connection and the HAPS UMRBus Interface Kit
Synopsys’ FPGA-based prototyping systems are used when synthesizable RTL models of the ASIC/system-on-chip design are available, allowing designers to develop software, verify SoC hardware and enable hardware/software integration before the silicon is taped-out. Hardware and software design teams can deploy HAPS® systems in a variety of roles in the SoC development cycle.

IP Development:
HAPS systems enable designers to confirm whether an RTL block is functionally correct at much higher speeds than traditional ASIC hardware emulation. HAPS systems ease initial system bring-up by executing a single IP module or subsystem with clock and reset synchronized with an HDL simulator. In addition, designers can use existing test benches for stimulus or in a free-running mode with PLL-sourced clocks to achieve the multi-megahertz performance required in real world I/O interfaces.

Hardware/Software Co-Development:
By using a high-performance prototype, software development can begin much sooner in the design process. A HAPS series system can achieve a typical clock frequency of 50MHz, making it feasible for SoC designs to execute the low-level firmware of the software stack, as well as the full operating system and even applications. When coupled with a Virtualizer™ virtual prototype, HAPS’ RTL subsystems run concurrently with SystemC/TLM-based processor models, creating a unique and powerful hybrid prototype that delivers the best of virtual and hardware prototyping methods.

End User Evaluation:
HAPS systems are light and portable. They can be powered with conventional power sources and quickly assembled in the field for customer demonstrations, industry conferences, “plug-fests”, and validation scenarios outside of the lab environment.

Synopsys’ FPGA-based prototyping solutions enable pre-silicon embedded software development and hardware/software integration of complete systems and subsystems at near real-time operating speeds using real-world interfaces. The HAPS® High-performance ASIC Prototyping System™ is designed to support all of your ASIC prototyping needs, including hardware/software co-development, proof-of-concept studies, IP development and end-user evaluations. HAPS FPGA-based prototyping system capabilities include:
  • Flexible, scalable and expandable system architecture – maximizes the reusability for multiple projects
  • Best-in-class quality and reliability – ensures the highest system performance and stability
  • HapsTrak standard – I/O connector standard that allows for backward and forward compatibility with previous and future generations of HAPS FPGA-based prototyping systems
  • High-speed Time-Domain-Multiplexing (TDM) – high-speed interconnect multiplexing increases bandwidth limiting effective capacity on FPGAs
  • Advanced verification functionality – includes co-simulation, transaction-based verification, and fast Universal Multi-Resource Bus (UMRBus) interface for high-speed design interaction and monitoring
  • DesignWare IP Portfolio – pre-tested IP configurations

Visit the HAPS FPGA-based prototyping webpage for more information.

Synopsys’ FPGA-based prototyping software tools provide engineers with design planning, logic synthesis, and debug, tools to address the largest system-on-chip (SoC) designs. Synopsys software for FPGA-based prototyping is applied by hundreds of design teams worldwide to maximize productivity when using the Synopsys HAPS series of FPGA-based prototyping systems or custom-built ASIC prototypes.

Comprehensive Design Automation and Debug for the HAPS Series of FPGA-Based Prototypes
If you're involved with system validation or hardware/software integration tasks then you're painfully aware of the demanding prototype project schedule that drives engineers to deliver operational prototypes within weeks or even days following the RTL "drop" from the design and verification team. There is little time for delay and this focus on reducing the "time-to-first" prototype has influenced the design and usage model for the HAPS design environment, ProtoCompiler.

ProtoCompiler delivers key features and benefits to address both rapid prototype bring-up and fast system performance:

  • Parallel processing, runtime optimizations, and short design iteration loops allow designers to deliver an operational HAPS system within days of RTL/IP availability
  • Quarter billion ASIC gate capacity to handle the highest-capacity HAPS Series systems ensures that you can support SoC/ASIC prototype projects today and in the future
  • Constraint-driven partitioning, high-speed time-domain multiplexing of FPGA I/Os, and system-level routing to maximize HAPS system clock performance
  • Flexible and high-capacity debug storage options for single or multi-FPGA debug maximizes visibility and sample rates available for HAPS systems
  • ARM AMBA and SCE-MI compatible transactor-level interfaces ease implementation of hybrid prototypes

For more information on Synopsys FPGA-based prototyping software tools for custom-built ASIC prototypes, see Synplify Premier and Certify.

FPGA-based prototyping hardware/software flow
FPGA-based prototyping hardware/software flow

Synopsys' offers the industry’s broadest portfolio of silicon-proven IP solutions for SoC designs. HAPS-compatible example designs are available for widely-used DesignWare IP products such as HDMI, MIPI, SATA, USB, audio subsystem and ARC processors.
Using DesignWare IP with HAPS eases common prototyping tasks, including:
  • Controller with PHY interoperability validation
  • System compliance tests
  • Subsystem integration
  • Firmware/software development

See live video demonstrations of DesignWare IP implemented on HAPS systems.

Get more detail about HAPS-series daughter boards designed for interface and SoC validation

A unified design and prototyping flow for SoC designs that integrates Synopsys DesignWare® IP eases the migration from the RTL/IP design to either an FPGA-based prototype or target ASIC silicon. The Synopsys coreConsultant tool guides the user from installation to a HAPS prototype using the ProtoCompiler software or an ASIC implementation using Synopsys Galaxy Implementation Platform.



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