ProtoCompiler 

The Fastest Way to Deliver Synopsys HAPS® Series FPGA-Based ASIC Prototypes 

Prototypes for pre-silicon system validation and hardware/software integration are essential for today's IP and SoC design teams. But development schedules are short and the brief time from "RTL drop" to test chip availability means that prototyping engineers are under tremendous pressure to deliver an operational prototype as fast as possible. ProtoCompiler is designed to minimize the effort and time required to bring-up and then deploy a Synopsys HAPS Series system for IP validation and software development with automation features for design planning, logic synthesis, debug, and connectivity to other verification environments like Synopsys VCS and ZeBu. The prototyping software is tightly integrated with the HAPS Series to deliver system performance unmatched by traditional "budget" circuit boards and FPGA design tools.
PDF ProtoCompiler DATASHEET (PDF)

 

ProtoCompiler features are designed to accelerate the time to an operational prototype. This focus on bring-up time and schedule improvement has improved processing time by up to 50 percent over competitive alternatives. ProtoCompiler's technology employs an efficient data model, compilers, and partitioning tools to improve productivity of engineers using the Synopsys HAPS Series of FPGA-based prototypes. The system allows short iteration loops at the key processing points in the design flow that have traditionally been time-consuming to complete. Compile and conversion of ASIC designs has been accelerated with fast compilers and clock-conversion specially designed for the HAPS Series. Generating a feasible design fit across multiple FPGAs has been fully automated with a quarter-billion ASIC gate partition engine that delivers results in minutes versus hours.

Reuse is a best-practice not only for ASIC design but for prototypes as well. The modular nature of the HAPS hardware architecture coupled with the incremental and hierarchical project management features of ProtoCompiler speed bring-up time by avoiding lengthy re-compile and place-and-route cycles. Prototype projects developed HAPS-DX and HAPS series systems are directly compatible and allow the prototyping team to integrate individual ASIC block or IP prototype projects into larger subsystems for full SoC validation scenarios.

Features Benefits

FPGA SYNTHESIS FOR HAPS

HAPS Clock Optimization (HCO)

ASIC-to-FPGA migration of gated clocks speeds prototype bring-up

DesignWare Library compatible

ASIC IP pre-validated with HAPS Series eases migration

Timing-driven synthesis

Maximizes system clock speed

SYSTEM PLANNING

System hardware targeting

Manage HAPS daughter boards, stacked systems, interconnect, and memories

High capacity design partitioning

Find a partition solution in minutes with multi-million ASIC gate designs

Hardware integration and reuse

Quickly assemble prototype modules into larger subsystems

DEBUG AND BRING-UP

Seamless multi-FPGA support

Debug logic regardless of where design modules are assigned

Synopsys Verdi/Siloti data exchange

Quickly import verification views and apply root cause analysis

High-capacity debug sample storage

Improve signal visibility and review longer periods of system operation

TRANSACTOR-BASED VALIDATION

AMBA transactors

Combine virtual and FPGA-based prototypes for earlier prototype availability

SCE-MI transactors

Connect to transaction-based verification environments like Synopsys VCS

ProtoCompiler vs. ProtoCompiler DX
Learn more about the differences between ProtoCompiler and ProtoCompiler DX and decide which is right for your prototyping project.

  ProtoCompiler DX ProtoCompiler
Packaging Included with HAPS-DX Sold separately
System Support HAPS-DX only HAPS-DX/70
FPGA LOGIC SYNTHESIS FOR HAPS
Multi-processing   4 per license
DesignWare Library Support
Hardware integration and reuse
Synopsys Design Constraint (SDC)  compatible
Infer memory from Unified Power Format (UPF)
Fast HDL compile mode
High quality synthesis results
SYSTEM PLANNING
System hardware targeting  
High-speed pin-multiplexing  
Multi-FPGA Partitioning  
Virtex-7 Super Logic Region (SLR) planning
Gated/Generated Clock Conversion
HAPS Clock Optimization (HCO)
Unified Power Format (UPF) Support
DEBUG AND BRING-UP
Seamless cross-FPGA visibility  
HAPS Deep Trace Debug (DTD) SRAM or SDRAM storage
HAPS Real Time Debug (RTD) logic analyzer assisted
Instrument and debug RTL source code
HAPS-aware troubleshooting
Synopsys Verdi/Siloti data exchange
Synopsys Formality logic equivalency check (LEC) support  
TRANSACTOR-BASED VALIDATION
AMBA Transactors Sold separately
SCE-MI Transactors Sold separately
HAPS System Prerequisite
  • HAPS Developer eXpress (HAPS-DX)
  • HAPS-70 Series
  • Mixed HAPS-70/DX Series systems
OS Support
For ProtoCompiler design-time features (design planning, logic synthesis, partitioning, etc.)
  • 64-bit Red Hat Enterprise Linux v5 or later
  • 64-bit SUSE Enterprise Linux v10 or later
For ProtoCompiler run-time features (RTL debug, HAPS bring-up utilities, etc.)
  • 64-bit Red Hat Enterprise Linux v5 or later
  • 64-bit SUSE Enterprise Linux v10 or later
  • 64-bit Windows 7 or later
System Requirements
  • 2 GB RAM
  • 4 GB free disk space for installation
  • Install from SolvNet download or DVD


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