|Synopsys Prototyping Solutions for ARM-Based Micro Server SoCs|
Synopsys prototyping technologies enable architecture design, application specific processor design and verification, early software development, customer enablement and SoC validation.
|VDK for Freescale™ Qorivva MCU|
The VDK for Freescale Qorivva MCU, built on Power Architecture® technology, is a so_ ware development kit using virtual prototypes of Qorivva based microcontrolllers.
|VDK for Renesas RH850 MCU|
The VDK for Renesas RH850 MCU is a software development kit using prototypes of the Renesas RH850 microcontroller family as a target.
|CoStart for Virtualizer Development Kit (VDK)|
CoStart for VDK will help your software development team get to market earlier with our team of experts.
|VDK Family for ARM® Processors|
Fast Software Bring-Up and Better Debug Control for ARMv7 and
ARMv8 Processor-based Designs
CoMET-METeor is a set of tools enabling the creation and deployment of virtual prototypes focused on accelerating real-time software development and system design/validation.
Virtual Prototypes are fast, fully functional software model of systems under development executing unmodified production code and providing a higher debugging/analysis efficiency.
|DesignWare® TLM Library|
The Synopsys DesignWare® TLM Library provides product development teams a comprehensive set of standards-based, tool-independent transaction-level models (TLMs) of DesignWare IP that serve as the building blocks of virtual prototypes.
The LTE/LTE-A Physical Layer Simulation Library is a set of ready-to-use simulation systems providing an executable specification of the 3 GPP standard. Being verified against Rohde & Schwarz signal generators, it provides unmatched increase in productivity for wireless physical layer system design.
SPW is the fastest path from innovation into implementation for digital signal processing systems, applying a model-based design approach.
|Synphony Model Compiler|
Synphony Model Compiler (SMC) is a high-level synthesis tool that supports model-based design environments such as Simulink/MATLAB from the Mathworks. The Synphony high-level IP model library allows algorithm and hardware engineers to quickly create synthesizable fixed-point, multi-rate algorithms in a familiar, high-level design environment. Then the SMC high-level synthesis engine can be used to create an optimized RTL implementation of these algorithms for ASIC or FPGA.
|Synphony C Compiler|
Synphony C Compiler is a high-level synthesis tool that provides an automated path from C/C++ in to silicon hardware. Using Synphony C Compiler, design teams can describe algorithms in high-level C/C++ and the quickly create optimized RTL implementations for FPGA or ASIC.
Synopsys® Processor Designer is an automated, application-specific embedded processor design and optimization environment that slashes months from processor hardware design time and from the creation of application processor-specific software development tools.
Synopsys Platform Architect is a SystemC TLM standards based graphical environment for capturing, configuring, simulating, and analyzing the system-level performance of next-generation SoC architectures.
|HAPS-600 High Capacity FPGA-Based Prototyping System|
The HAPS-600 series, based on the latest Virtex-6 FPGA devices, provides a modeling capacity of up to 81 million ASIC gates equivalent and has a patented programmable interconnect technology that delivers the high performance system speed expected of an FPGA-based prototyping product.
|HAPS-64 Virtex-6 Motherboard|
The HAPS-64 system is optimized for the highest possible performance. Containing four Xilinx Virtex-6 FPGAs, a single HAPS-64 board can accommodate up to 18 million ASIC gates.
|HAPS-62 Virtex-6 Motherboard|
The HAPS-62 system is a high-performance multi-FPGA board containing two Xilinx Virtex-6 FPGAs. A single HAPS-62 board can accommodate up to 9 million ASIC gates; for larger capacity designs the board can be expanded by connecting additional motherboards and/or daughter boards using the HapsTrak standard.
|HAPS-54 Virtex-5 Motherboard|
The HAPS-54 FPGA-based prototyping system contains four Xilinx Virtex-5 FPGAs. A single HAPS-54 board can accommodate up to 8 million ASIC gates.
|HAPS-52 Virtex-5 Motherboard|
The HAPS-52 FPGA-based prototyping system contains two Xilinx Virtex-5 FPGAs. A single HAPS-52 board can accommodate up to 4 million ASIC gates
|HAPS-51T Virtex-5 Motherboard with High-Speed SerDes Links|
The HAPS-51T FPGA-based prototyping system contains one Xilinx Virtex-5T FPGA. A single HAPS-51T board can accommodate up to 2 million ASIC gates
|HAPS-51FXT Virtex-5 Motherboard with High-Speed SerDes Links|
The HAPS-51FXT FPGA-based prototyping system contains one Xilinx Virtex-5 FXT FPGA. The HAPS-51FXT is specifically designed to support integration of high-speed SerDes protocols such as PCI Express Gen 2
|HAPS-51 Virtex-5 Motherboard|
The HAPS-51 FPGA-based prototyping system contains one Xilinx Virtex-5 FPGA. A single HAPS-51 board can accommodate up to 2 million ASIC gates
|SuperSpeed USB 3.0 Transaction-Level Models|
The SuperSpeed USB 3.0 transaction-level models (TLM) enable pre-RTL and pre-silicon software development, verification and architecture exploration. The models are TLM representations of the Synopsys DesignWare® SuperSpeed USB 3.0 Device and xHCI Host Controller.
System Studio is the high performance model-based algorithm design and analysis tool, combining unmatched simulation performance and highest modeling efficiency, plus industry's best integration into the implementation design and verification flow. Algorithm design is an essential task in signal processing applications such as wireless telephony, multimedia codecs, DSL and cable modems.